JPH0289286A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve an operation speed by providing a pulse width controlling circuit to change the pulse width of an address change detection signal with the use of a control signal being obtained from a write-enable signal for an address change detection signal synthesization circuit. CONSTITUTION:The width of a one-shot pulse is decided by the delaying time of a delay circuit and is the minimum value of the pulse width of ATD to be finally obtained. These signals 1-3 are received by the gate electrodes of NMOS 31-33. When a positive pulse is generated in at least one of the ATDn, the NMOS being connected to a signal line is made into a conductive state, the potential of an intermediate signal 11 is decreased to a grounding potential after pulse synthesization, after the lapse of the time of the pulse width, the NMOS is cut off again, and the potential of a signal 11 is increased again. The gate electrode of PMOS 41 is grounded to be constantly in the conductive state, the PMOS 41 constitutes the pulse width control circuit, and the pulse width control signal is inputted into the gate electrode. Thus, the unnecessary waiting time at the time of read or write can be eliminated.

Description

[Detailed description of the invention] [Industrial application field] Regarding internally synchronous random access memory.

[Conventional technology]

Conventionally, a circuit such as that shown in Japanese Patent Publication No. 60-57156 has been used to detect changes in external input address signals and achieve internal synchronization. A conventional example is shown and explained in FIGS. 3(a) and 3(b).

In FIG. 3(a), 1.2.3 is the address change detection signal for 1 bit of the external input address signal (hereinafter, the first
The address change detection signal for the second bit is ATD1, the address change detection signal for the second bit is ATD2, etc.
The bit number is shown following rATDJ. 12 is an address change detection signal (hereinafter simply referred to as ATD) which is a combination of all ATDn. Internal synchronization is achieved using the ATD.

31, 32, and 33 are N-channel insulated gate field effect transistors (hereinafter referred to as 8MO3), and each A
In response to the signal level of the power supply voltage of TDn, the signal level of 11 is set to the ground voltage.

41 is a P-channel insulated gate field effect transistor (hereinafter referred to as PMO3), and when the gate is grounded and all NMO8 of 31 to 33 are cut off, 11. Set the signal level to the power supply voltage. 31～
33 and 41 constitute a NOR circuit.

21 is an inverter for shaping the waveform of the 11 signals.

FIG. 3(b) shows the timing of the external input address signal 101, the write enable signal (hereinafter referred to as WE) 5, and the signals of each portion of FIG. 3(a). The same operation is performed during read, write, and write recovery. 101, pulses 1 to 3 are generated, and the circuit of FIG. 3(a) synthesizes the signals into an inverted pulse 11 with a sharp fall and a slow rise.
Shape the waveform to TD. The ATD is used to erase previous old data on the data line (hereinafter, this operation is referred to as equalization) and to control the sense amplifier circuit, write gate, etc.

[Problem to be solved by the invention]

However, the period required for equalization during read, or
Let tl be the ATD pulse width necessary to confirm data from the memory cell when the sense amplifier is on, and let tl be the ATD pulse width required to confirm data from the memory cell when the sense amplifier is in the on state.
If the TD pulse width is tl, if tl is longer than 2, the ATD pulse width is determined by tl, and if the write pulse is longer than necessary and tl is longer than tl, then AT
The pulse width of D is determined by tl, which has the problem that the access time becomes longer than the original operation time.

The purpose of the present invention is to change the ATD pulse width during reading and writing, ensure the optimum ATD pulse width for each logic state, eliminate unnecessary operating time as described above, and increase operating speed. An object of the present invention is to provide an improved semiconductor memory device.

[Means to solve the problem]

The semiconductor memory device of the present invention includes an address change detection circuit that detects a change in each external input address signal and generates a pulse, and an address change detection signal that synthesizes the outputs of a plurality of the circuits to obtain an address change detection signal. A semiconductor memory device having a synthesis circuit, characterized in that the address change detection signal synthesis circuit is provided with a pulse width control circuit that changes the pulse width of the address change detection signal using a control signal obtained from a write enable signal. shall be.

[For production]

With the above configuration, the optimum ATD pulse width is ensured for each logic state during read and write.

〔Example〕

An embodiment of the present invention is shown in FIG. 1 and will be described.

First, in Figure 1(a), 1.2.3 is ATDI,
ATD2 and ATDn are one-shot pulses in which changes in each bit of an externally input address signal are detected using a delay circuit or the like. The pulse widths of these signals are determined by the delay time of the delay circuit, and are also the minimum value of the finally obtained ATD pulse width. These signals 1.2.3 are received at the gate electrodes of NMOs 531, 32, and 33. When a positive pulse occurs in at least one of ATDn, NMO5 connected to the signal line becomes conductive, lowering the potential of 11 to the ground potential, and after the pulse width time has elapsed, NMO8 becomes conductive again. There is a cutoff, and the potential of 11 rises again. The gate electrode of the PMO 541 is grounded and always in a conductive state. PMO34
1 constitutes a pulse width control circuit, and a pulse width control signal is input to the gate electrode. Due to the action of these PMO3, the potential of 11 is weakly pulled up to the power supply potential,
When all of the NMOs 3 are cut off, 11 rises to the power supply potential. The falling speed and rising speed of the potential in 11 are 3
It is determined by the driving abilities of 1 to 33, 41, and 42.

In particular, the rate of rise is determined solely by 42 and 41. That is, when 41 is in the cutoff state by the pulse width control signal, the increase in the potential of 11 depends on the driving ability of only 42, but on the other hand, when 41 is in the conductive state due to the signal, both 41 and The rate of increase in the potential of 11 is determined by the sum of the driving capacities of 42.

The ratio of the rising speed of the potential of 11 depending on the state of 41 is arbitrarily determined by the driving ability of 41 to 42, that is, the transistor size. Finally, the 11 signals are waveform-shaped by a waveform shaper 21 using an inverter or the like to obtain 12 ATDs.

The difference in potential rise speed of 11 becomes the difference in the arrival time to the logical threshold value of 21, and therefore the pulse width can be changed as necessary.

FIG. 1(b) shows the timing of the external input address signal (hereinafter referred to as address signal) 101 and the potentials of each part of the circuit of FIG. 1(a). When at least one bit of the address signal changes, pulses 1 to 3 are generated as shown. If a signal in phase with W100 is selected as the pulse width control signal, three states of timing can be considered: read, write recovery, and write, as shown in FIG. 1(b).

At the time of reading, WE is the power supply potential, so 6 is also the power supply potential, and as mentioned above, the rate of increase in the potential of 11 is slow,
Therefore, the pulse width t1 of the ATD signal 12 becomes longer.

On the other hand, at the time of write recovery and write, WE is at the ground potential, so 6 is also at the ground potential, and as mentioned above, the rising speed of the potential at 11 is sharp, and therefore the pulse width t2 of the ATD signal 12 is shorter than tl. .

6 moves as during write recovery, equalization is performed to ensure time for write recovery. t
l is adjusted to the time required for this write recovery, and tl is adjusted to the time required for equalization during read.

Further, another embodiment is shown in FIG. 2 and will be described.

In this embodiment, the relationship between the lengths of tl and tl in FIG. 1(b) is reversed.

In FIG. 2(a), 5 is WE, and inverters 22 and 23 are used to obtain a pulse width control signal 6 having an opposite phase to WE.
．． 24 is used. PMOS 41 is a pulse width control circuit, and 42 is a load transistor. NMO3 31 to 33 are for receiving ATDl, ATD2, and ATDn and controlling the signal 11. 11 is waveform-shaped by the inverter 21 and becomes an ATD of 12.

In FIG. 2(b), since the pulse control signal 6 is a reverse phase signal of WE5, the potential rise speed of 11 is slower during write recovery and write than during read.
Therefore, in the 12 ATD signals, the latter pulse width t2 is longer than the former pulse width t1. In this embodiment as well, tl and tl are adjusted in the same way as in the first embodiment.

〔Effect of the invention〕

Due to the above action, the pulse width of ATD during read and write can be ensured to be the optimum length for the ability of each logic state of the memory circuit, thereby eliminating unnecessary pulse width during read or write. This has the advantage of eliminating waiting time and improving operating speed.

[Brief explanation of the drawing]

FIG. 1(a) is a circuit diagram showing one embodiment of the present invention.
FIG. 1(b) is a timing chart of signals of each part in FIG. 1(a). FIG. 2(a) is a circuit diagram showing a second embodiment of the present invention,
FIG. 2(b) is a timing chart of signals of each part in FIG. 2(a). Figure 3(a) is a circuit diagram according to the prior art, Figure 3(b)
FIG. 3(a) is a timing chart of signals of each part. 1... Address change detection signal of the 1st bit external input address signal (ATD l) 2... Address change detection signal of the 2nd bit external input address signal (ATD 3... Arbitrary bit Address change detection signal (ATD n) of external input address signal ・Write enable (active low) ・Pulse width control signal ・Intermediate signal after pulse synthesis ・Address change detection signal (ATD) 5・・11・φ12・・21 φ22・・23・No.24・・316・32・・33・・41・・42・・101・・Waveform shaping circuit・Inverter・Inverter・Inverter NMOS・MNOS φNMOS・PMOS (Pulse width control circuit)・PMOS (Load transistor) ・External input address signal or more Applicant: Seiko Epson Corporation Representative Patent attorney: Masahiro Kamiyanagi (and 1 other person) Whistle diagram 2 + a
) Figure 1 (b) Figure 3 (a) Figure 3 (b)

Claims (1)

[Claims] A semiconductor memory device having an address change detection circuit that detects changes in individual external input address signals and generates pulses, and an address change detection signal synthesis circuit that synthesizes the outputs of a plurality of such circuits to obtain an address change detection signal. A semiconductor memory device according to claim 1, wherein the address change detection signal synthesis circuit is provided with a pulse width control circuit that changes the pulse width of the address change detection signal using a control signal obtained from a write enable signal.