JPH0287531A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make a CoSi2 film smaller than the junction depth of a source.drain part, and prevent the generation of leak current in a junction layer by a method wherein, after a gate part and the source.drain part are formed, a CoSi film is formed by transforming each of the parts into silicide, and W is deposited on each part via the CoSi2 film. CONSTITUTION:On an Si substrate 1, a gate part 3 composed of N<+> type polysilicon is formed; by implanting As<+> on the Si substrate 1, an N<+> type source.drain part 4 is formed; Co is deposited on the substrate 1; by heat treatment, the gate electrode 3 and the source.drain part 4 are transformed into silicide: not-yet-reacted Co of a side-wall part 5 in the gate part 3 is eliminated, and a CoSi2 film 6 of 200-300Angstrom thick is formed. The depth of the source.drain part 4 is about 0, 15-0.2mum. In conventional arts, a wiring layer is formed only by a silicide film of CoSi2, so that the film thickness is required to be 1500-2000Angstrom or more. By the effect of silicide, the generation of leak current in the junction layer can be avoided.

Description

[Detailed Description of the Invention] (a) Industrial Application Field This invention relates to a method of manufacturing a semiconductor device, and more specifically, with the miniaturization of MOS type devices, the wiring portion of a transistor is made of a high melting point metal to reduce resistance. The present invention relates to a method for creating a low resistance gate part and source/drain part.

(b) Conventional technology Conventional methods of this kind include (i) forming a silicide film of a high-melting point metal such as Co or Ti, and (ii) selectively growing it using W to form source and drain layers. Department,
It has been proposed to attach it to the gate.

Figure 4 shows the mask method.

In FIG. 4, a gate electrode 23 made of n-polysi is formed on a Si substrate 21 via a SiO* film 22 [see FIG. Forming the drain 24 [Fig. 4 (
See b)]. Next, Co (or Ti) is deposited on the substrate 21.
25 [see FIG. 4(c)], then heat treatment is performed to silicide the gate electrode 23 and the source/drain 24 to form CoS 11 (or Ti5it).
A silicide film 26 consisting of is formed, and unreacted CO in the sidewall portion 27 is removed by subsequent selective etching to form a wiring portion [see Fig. 4(d) @]
.

In this way, by siliciding Co (or Ti), a transistor with a salicide structure can be created, and the resistance of the gate electrode 23 and source/drain 24 can be reduced.

On the other hand, in the latter method, as shown in FIG. 3(a), a gate electrode 23 is created, and a source/drain 24 is created (see FIG. 3(b)). After that, the gate electrode 23 is formed using the CVD method. A W film 28 is selectively deposited on the electrode 23 and source/drain 24 [see FIG. 3(c)].

(c) Problems to be solved by the invention However, in the former method, it is necessary to reduce the sheet resistance to 107 or less in order to achieve high-speed devices.
Even if low-resistance silicide (specific resistance: 15 μΩ·cm) such as Siy (or TiSit, etc.) is used, a silicide film thickness of 1500 to 2000 Å or more is required.

In submicron devices, the depth of the source/drain junction is about 0.15 to 0.2 μm, so silicidation poses a problem of leakage current in the junction layer.

On the other hand, in the latter method, the problem with the selective growth method is that S
There is a large possibility that encroachment 29 will enter the tO2/Si interface [see Figure 2], causing junction leakage.

Furthermore, after depositing the interlayer insulating film, it is necessary to perform a heat treatment at about 900 to 1000°C to flatten it, but at this time, the WI
A silicidation reaction of IIE28 occurs and the characteristics become unstable.

From the above, with the conventional technology, it is difficult to reduce the resistance of the gate portion and the source/drain portion in a self-aligned manner.

(d) Means for Solving the Problems This invention is a method of laminating cobalt (Co), a high-melting point metal, on a silicon substrate on which a gate portion made of polysilicon is disposed via a source/drain portion and a silicon oxide film. Then, the source/drain part and the gate part are silicided by heat treatment to form a cobalt silicide film (Co) having a thickness substantially smaller than the junction depth of the source/drain part.
After that, selective etching is performed to remove unreacted CO on the sidewall portion of the gate portion, and then W, a high melting point metal, is selectively grown on the source/drain portion and the gate portion via a Co51t film. This is a method of manufacturing a semiconductor device, which comprises stacking layers to form thermally stable low resistance gate portions and source/drain portions.

That is, this invention is based on Metal/MeLal 5i
It has a three-layer structure of licide/Si,
Generally, in a silicide film of a high melting point metal, St is the main diffusion species, so when heat treatment is performed, the metal in the upper layer becomes silicide.

However, in the case of Co51z, CO is the main diffusing species, and S
i is difficult to diffuse. Therefore, if W, which is a metal that is less likely to be silicided than CO, is brought to the upper layer, it can be expected that silicide formation of W can be prevented during heat treatment.

In this invention, a predetermined thickness (for example, 200 to 300 layers) of Co is formed by a silicidation reaction after forming the source/drain.
By forming a layer of S+, W was deposited on the layer by selective growth.

In this invention, forming a cobalt silicide film having a thickness substantially smaller than the junction depth of the source/drain portion means that ρj, for example, when the junction depth of the source/drain portion is approximately 0.15 to 0.2 μm, Designed to prevent leakage current from occurring in the bonding layer even when silicided 2
This means forming a CoS it film of 00 to 300 people.

(e) After forming the working gate part and the source/drain part, each of these parts is silicided to form a Co51t film of a predetermined thickness, and then W is deposited on each part through the CoSit film. Therefore, since the Co51t film is smaller than the junction depth of the source/drain part, it can reduce the amount of encroachment into the Si substrate, and the Co51s can also prevent encroachment from entering the Si substrate interface after selective growth of W. This eliminates the risk of leakage current occurring in the bonding layer.

Moreover, even if heat treatment is performed after selectively growing W, Co
Since the 51t layer acts as a barrier layer to prevent W from becoming silicide, a thermally stable low resistance gate portion and source/drain portion can be created.

(f) Example The present invention will be described in detail below based on embodiments shown in the figures.

Note that this invention is not limited by this.

In FIG. 1, the MOS type device created by this method has a metal/metal interconnection having a two-layer structure of W film 7/Co51T film 6 in order from the top, as shown in FIG. 1(C). It mainly consists of a three-layer structure of silicide/silicon.

The manufacturing method will be explained below.

First, nPo1y is deposited on a Si substrate 1 via a 5iOz film 2.
A gate portion 3 made of Si is formed, and As'' is implanted onto the Si base substrate to form a source/drain portion 4 of n'' [see FIG. 1(a)]. Co
The gate electrode 3 and the source/drain part 4 are silicided by heat treatment, and the unreacted Co in the sidewall first part 5 of the gate part 3 is removed by subsequent selective etching.
A 1t film 6 is formed [see FIG. 1(c)]. Here, the junction depth of the source/drain part 4 is 0.15 to 0.2 μm.
Conventionally, the wiring part was formed only with a Co51t silicide film, so the film thickness was 1500 to 2000.
Å or more is required, and silicidation can solve the problem of leakage current in the bonding layer.

Further, W is deposited on the CoS it film by a selective growth method to form a W film 7 having a thickness of 1000 to 2000 nm.

Finally, after depositing the interlayer insulating film, this is
A heat treatment is performed at approximately 000° C. to flatten the surface. At this time, Co is the main diffusion species in Co51t, and Si
Since W is a metal that is difficult to diffuse, and W is a metal that is less likely to be converted into silicide than Co, the W film 7 is disposed directly above the CoS L film 6, and there is no possibility that a silicidation reaction of W will occur even if the above heat treatment is performed. This is not the case, and it is possible to prevent the characteristics from becoming unstable.

In this way, a transistor with a salicide structure is created by silicidation of Co, and W is deposited by selective growth on the source/drain portion and gate portion, thereby making it possible to create a thermally stable low resistance gate and source/drain.

(G) Effects of the Invention According to the present invention, after forming the gate portion and the source/drain portion, these portions are silicided to form a C of a predetermined thickness.
Since an o51t film was formed and W was then deposited on each of the above parts via a Co51t pattern, Co51t
Because the film is smaller than the junction depth of the source/drain part, S
In addition to reducing encroachment on the i-substrate, the Co5L film prevents encroachment from entering the interface of the Si substrate after the selective growth of the W film, thereby eliminating the risk of leakage current occurring in the bonding layer. .

In addition, after selectively growing the W film, heat treatment is performed and C
Since the o5L layer acts as a barrier layer to prevent silicidation of the W film, it is possible to create a thermally stable low resistance gate portion and source/drain portion.

[Brief explanation of the drawing]

Fig. 1 is a manufacturing process explanatory diagram for explaining one embodiment of the present invention, Fig. 2 is an explanatory diagram of main part groove formation showing a conventional example, and Figs. 3 and 4 are respectively for explaining the conventional example. It is a manufacturing process explanatory diagram. DESCRIPTION OF SYMBOLS 1... Si substrate, 2... Silicon oxide film, 3... Gate electrode, 4... Source/drain, (n part, 5... ... Side wall portion, 6 ... CoSit film, 7 ... W film.

Claims (1)

[Claims] 1. Cobalt (Co), a high melting point metal, is laminated on a silicon substrate on which a source/drain part and a gate part made of polysilicon are disposed via a silicon oxide film, and the source/drain part and gate part are formed by heat treatment. A cobalt silicide film (CoSi_2) that has been silicided and has a film thickness substantially smaller than the junction depth of the source/drain region.
After that, unreacted Co on the sidewalls of the gate area was removed by selective etching, and W, a refractory metal, was deposited by selective growth on the source/drain and gate areas via a CoSi_2 film. A method for manufacturing a semiconductor device comprising forming a thermally stable low resistance gate portion, source/drain portion.