JPH0285482U - - Google Patents
Info
- Publication number
- JPH0285482U JPH0285482U JP16493088U JP16493088U JPH0285482U JP H0285482 U JPH0285482 U JP H0285482U JP 16493088 U JP16493088 U JP 16493088U JP 16493088 U JP16493088 U JP 16493088U JP H0285482 U JPH0285482 U JP H0285482U
- Authority
- JP
- Japan
- Prior art keywords
- display
- address
- storage
- storage means
- display information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図は本考案実施例の基本構成を示すブロツ
ク図、第２図は本考案実施例の具体的な構成を示
す回路図、第３図は本考案実施例の表示形態を示
す説明図、第４図は第２図に示すビデオメモリ３
のメモリ構成を示すメモリマツプ、第５図は第２
図に示すアドレス変換メモリ１２のメモリ構成を
示すメモリマツプ、第６図は本考案実施例の表示
アドレスとビデオメモリ３の読出しアドレスの対
応関係を示す説明図、第７図は第２図に示すＣＰ
Ｕ１１が実行する制御手順を示すフローチヤート
、第８図は従来例の回路構成を示す回路図である
。
１，１１…ＣＰＵ、２…表示器用コントローラ
、３…ビデオメモリ、４…文字発生器、５…並直
列変換器、６…駆動回路、７…表示器。
FIG. 1 is a block diagram showing the basic configuration of the embodiment of the present invention, FIG. 2 is a circuit diagram showing the specific structure of the embodiment of the present invention, and FIG. 3 is an explanatory diagram showing the display form of the embodiment of the present invention. Figure 4 shows the video memory 3 shown in Figure 2.
A memory map showing the memory configuration of
6 is an explanatory diagram showing the correspondence between display addresses and read addresses of the video memory 3 in the embodiment of the present invention; FIG. 7 is a memory map showing the memory configuration of the address conversion memory 12 shown in FIG.
FIG. 8 is a flowchart showing the control procedure executed by U11, and is a circuit diagram showing the circuit configuration of a conventional example. DESCRIPTION OF SYMBOLS 1, 11...CPU, 2...Display controller, 3...Video memory, 4...Character generator, 5...Parallel-serial converter, 6...Drive circuit, 7...Display device.
Claims (1)
に表示するために予め記憶する第１記憶手段と、 前記表示情報の前記表示画面上の表示位置を指
示する指示手段と、 前記第１記憶手段における前記表示情報の格納
アドレスを前記指示手段により指示された表示位
置に対応して記憶し、リフレツシユアドレスに応
じて、当該格納アドレスを読み出しアドレスとし
て前記第１記憶手段に順次に出力する第２記憶手
段と、 を具えたことを特徴とする表示装置。[Claims for Utility Model Registration] First storage means for storing display information of one or more screens in advance for displaying on the display screen; and instruction means for instructing the display position of the display information on the display screen. and storing the storage address of the display information in the first storage means in correspondence with the display position instructed by the instruction means, and read out the storage address as a read address according to the refresh address. A display device comprising: a second storage means for sequentially outputting data;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16493088U JPH0285482U (en) | 1988-12-20 | 1988-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16493088U JPH0285482U (en) | 1988-12-20 | 1988-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0285482U true JPH0285482U (en) | 1990-07-04 |
Family
ID=31450963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16493088U Pending JPH0285482U (en) | 1988-12-20 | 1988-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0285482U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61215585A (en) * | 1985-03-20 | 1986-09-25 | 富士通株式会社 | Multi-screen display method of display device |
| JPS61295594A (en) * | 1985-06-25 | 1986-12-26 | 沖電気工業株式会社 | Control system for display unit |
| JPS6225785A (en) * | 1985-07-26 | 1987-02-03 | アルプス電気株式会社 | Display control processing system for multiple window |
-
1988
- 1988-12-20 JP JP16493088U patent/JPH0285482U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61215585A (en) * | 1985-03-20 | 1986-09-25 | 富士通株式会社 | Multi-screen display method of display device |
| JPS61295594A (en) * | 1985-06-25 | 1986-12-26 | 沖電気工業株式会社 | Control system for display unit |
| JPS6225785A (en) * | 1985-07-26 | 1987-02-03 | アルプス電気株式会社 | Display control processing system for multiple window |
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