JPH0283936A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To form an offset region without damaging source/drain regions by forming a thermal oxide film on a polysilicon gate electrode and by forming the offset region utilizing this thermal oxide film. CONSTITUTION:After forming a polysilicon gate electrode 4, a resist film 11 is eliminated and thermal oxidation is performed for forming a thermal oxide film 13 on the gate electrode 4. With this thermal oxide film 13 as a mask, doping in high concentration with an N-type dopant (normally arsenic) is performed, the thermal oxide film 13 on the gate electrode 4 is eliminated, and doping in low concentration with an N-type dopant (phosphor) is performed for providing a low-concentration region 6. Thus, only the processes for thermal oxidation and elimination of the thermal oxide film 13 are added for forming an offset region without making the process to be complex, thus preventing the source/drain regions from being damaged.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides a gate electrode made of polysilicon, and a low concentration region called an offset region between a high concentration region including a contact portion of a source/drain region and a channel region. The present invention relates to a method of manufacturing a MOS transistor having the following.

[Conventional technology]

In order to achieve high density integrated circuits, MOS transistors have been scaled down and highly integrated circuits of N-MOS and C-MOS transistors using design rules with channel lengths of 2 μm or less have been realized.

In the above design level N-MOS transistor,
From the viewpoint of reliability, a structure is generally adopted in which a low concentration region of approximately 0.2 μm length, called an offset region, is provided between a high concentration region including a contact portion in the source/drain region and a channel region. This structure is called LDD (Ljght2y
It is called Doped Drain) n4 construction.

FIG. 2 shows an example of an N-MOS transistor with an LDD structure.

In the figure, 1 is a P substrate, 2 is a field oxide film, and 3 is an r
-) oxide film, 4 is a polysilicon r-) electrode, 5 is an n-concentration region, 6 is an n-low concentration region, and 7 is a CVD oxide film.

The above-mentioned n low concentration region (offset region) is difficult to form using conventional photophosphorography technology due to the alignment accuracy of the aligner, the resolution of the Lennost, etc., so various methods have been developed to solve this problem. Proposed.

FIG. 3 shows an example of a method for making a conventional LDD.

A polysilicon film is formed on the field oxide film 2 and gate oxide film 3 formed on the surface of the P substrate 1, a large amount of P is doped by diffusion or ion implantation to lower the sheet resistance, and nine turns are performed using Lenost 11 as a mask. Then, a polysilicon gate electrode 4 is formed, and a low concentration N-type dopant is doped using this r-) electrode 4 as a mask [Fig.
).

Next, a CVD oxide film 1 is applied to the surface of the wafer after the above steps.
2 [Figure (b)], and this CVD film 12 is coated with Ri.
G (reactive ion etching; anisotropic etching) and CVD on both sides of the gate electrode 4.
Form the spacer for Jakuka Membrane Work 2 [Figure (C)]. Using this spacer 12 as a mask, dope with a high concentration of N-type doping, remove the spacer 12 and resist 11, and form a CVD 7G film 7 (PSG) on the surface (Figure C)
].

Through the above steps, a layer high concentration region 5 and an nti 11 degree region 6 are formed.

Since the steps other than those described above are generally well known, their explanation will be omitted.

[Problem to be solved by the invention]

The conventional method described above is CVD to form a spacer that serves as a doping mask for a high concentration region.

With the introduction of the RIE process, the process becomes more complex, and
There is a problem in that the source/drain regions are damaged during the RIE process.

The present invention was made to solve the above problems, and
It is an object of the present invention to provide a method that does not cause damage to source/drain regions without complicating the process too much.

[Means to solve the problem]

The method of the present invention focuses on the fact that in thermal oxidation, the oxidation rate of dope and arsenic on silicon with high concentrations of phosphorus and arsenic is much faster than on silicon with low concentrations. A thermal oxide film with a thickness of approximately 0.2 μm is used to form the offset region.

〔Example〕

FIG. 1 shows an embodiment of the invention.

The process up to the state shown in the figure (,) is the same as the conventional normal process.

A field oxide film 2 and a gate oxide film 3 are provided on the surface of the P substrate 1, polysilicon is deposited on the oxide films 2 and 3 by the CVD method, and a large amount of P is doped by diffusion or ion implantation. /cyn3 order), and a polysilicon gate electrode 4 is formed by photolithography and etching [Figure (a)].

Next, the resist 11 is removed, thermal oxidation is performed at about 900°C, and a film with a thickness of about 0.2 μm is formed on the polysilicon gate electrode 4.
A thermal oxide film 13 is formed.

A thermal oxide film 13 is formed on the polysilicon gate electrode 4 with a concentration on the order of 1020/crn3 at an oxidation rate approximately 3 to 4 times that of low-concentration silicon with a concentration on the order of 1016/(7)3, for example. .

Using this thermal oxide film 13 as a mask, an N-type dopant (usually arsenic) is doped at a high concentration.

(10157,,,2 orders) [Figure (b)].

Next, the thermal oxide film 13 on the gate electrode 4 is heated using hydrogen monofluoride.
Using the gate electrode 4 as a mask, an N-type dopant (phosphorus) is doped at a low concentration (usually on the order of 10 to 10 cm) [Figure (c)), and the thickness of the thermal oxide film 13 is reduced to 0.
．． A low concentration region 6 (offset region) regulated to 2 μm and approximately 0.2 μm long is provided [Figure (d)].

After that, a CVD oxide film 7 (PSG) is formed on the surface [
Figure (,) ] The steps of opening a window at the electrode extraction portion, depositing a metal film such as aluminum, and forming the electrode are exactly the same as the conventional method.

In the above method, the simple steps of thermal oxidation and thermal oxide removal are added to form the offset region, and the process is not complicated. No area is damaged.

〔Effect of the invention〕

As explained above, the present invention simplifies the process compared to conventional methods, eliminates the need for expensive equipment, leads to cost reduction, and eliminates damage to the source and drain regions. There is an effect.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing one embodiment of the present invention, Fig. 2 is an LD
An explanatory diagram showing an example of a D-structure N-MOl transistor,
FIG. 3 is an explanatory diagram showing an example of a method for making a conventional LDD structure. ■...P substrate, 2...field oxide film, 3...
Gate oxide film, 4... Polysilicon gate electrode, 5.
...n+ high concentration area, 6...0 low concentration area, 7...
CVD plating film SG), 11... Renost, 1
3...Thermal oxide film. The same symbols in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] An MO in which the gate electrode is made of polysilicon and has a low concentration region called an offset region between the high concentration region including the contact part of the source/drain region and the channel region.
In the manufacturing method of an S transistor, a polysilicon film is formed on a field oxide film and a gate oxide film formed on the surface of a silicon substrate, and a gate electrode is formed by doping a large amount of P (phosphorus) by diffusion or ion implantation and then patterning. Thermal oxidation at approximately 900°C reduces the film thickness to approximately 0.
．． A 2 μm thick silicon oxide film is formed, and using this silicon oxide film as a mask, high concentration regions of the source/drain region are formed.After removing the silicon oxide film with hydrogen fluoride, the source/drain region is formed using the gate electrode as a mask. 1. A method for manufacturing a MOS transistor, comprising forming a low concentration region.