JPH0283584A - Double speed linear sequential scanning circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix type image display device, and in particular, to driving two or more rows of pixels in a display means during one normal horizontal scanning period. The present invention relates to a double-speed line sequential scanning circuit that performs the following using a line sequential scanning method (the line sequential scanning method will be explained in detail later).

[Conventional technology]

In general, color television image display devices with a screen size of about 6 inches or more require particularly high resolution.
When inputting an NTSC image signal, it is necessary to display approximately 480 effective horizontal scanning lines, and therefore, in the case of an active matrix type television image display device, approximately 480 vertical pixels are required. . Also, NTS
Since the C format image signal is an interlaced image signal with a frame frequency of 30Hz (field frequency 607),
In the active matrix type television image display device described above, if a conventional driving method is used in which only one row of pixels is selected during one horizontal scanning period (hereinafter sometimes referred to as one horizontal scanning period), each A pixel is selected once per frame and driven with an image signal corresponding to that pixel.

Here, in this image display device, if a liquid crystal element is used as a display element (that is, a liquid crystal panel is used as a display means), it is necessary to perform AC drive in terms of its lifespan (liquid crystal elements do not require AC drive). (If this is not done, its life will be shortened.) Therefore, the polarity of the image signal must be reversed for each frame, but at this time, the AC driving frequency of the liquid crystal element is 1/2 of the frame frequency.
5 Hz (i.e., positive polarity in the first frame).

This is because the next frame has a negative polarity, and one cycle consists of two frames. ). However, if a liquid crystal element is driven with AC at such a frequency of 157, flicker will often occur because the frequency is low, so it is necessary to ensure that the AC driving frequency of the liquid crystal element is at least 30 Hz. .

In this way, in order to set the AC drive frequency to 30Hz, each pixel is not selected once per frame, but twice, that is, once per field (one frame consists of two fields). The polarity of the image signal may be inverted and driven for each field. However, the number of effective scanning lines in one field is approximately 240, and therefore, when driving a liquid crystal panel with approximately 480 vertical pixels at such a frequency of 307,
Two rows of pixels must be selectively driven during the horizontal scanning period.

In this way, pixels for two rows are selectively driven during one horizontal scanning period, all pixels of the liquid crystal panel are selectively driven once per field, and the AC driving frequency of the liquid crystal element is set to 3, OH.
An example of an active matrix image display device with z is
It is discussed in IEICE Technical Report Vol. 84, No. 159 (1982), pages 21 to 26.

By the way, in an active matrix type image display device, as a method of arranging color filters for colorization, a triangular color filter arrangement having little directional dependence and high resolution is advantageous. Triangular color filter arrangement is a stripe arrangement in which pixels of the same color are arranged vertically on the screen and pixels of the three primary colors R, G, and H are arranged in order in the horizontal direction of the screen, and the pixel positions of the three primary colors are arranged in each row. This is an arrangement method in which the pixels are shifted by 1.5 pixels in the horizontal direction, and three adjacent pixels form a triangle using the three primary colors. An example of an active matrix type image display device using such a triangular filter arrangement is the one described in Japanese Patent Application Laid-open No. 141492/1983.

[Problem to be solved by the invention]

Among the above-mentioned conventional technologies, in the former proposed example, 1
In order to sequentially drive two rows of pixels during a horizontal scanning period, an A/D converter, a digital memory as a field memory, a D/A converter, etc. are used to first generate an increment image signal through digital processing. A so-called double-speed conversion is performed on the image to obtain a non-interlaced image signal, and the non-interlaced image signal is input to a horizontal scanning circuit.
It was driving the LCD panel.

Therefore, in this prior art, it is necessary to increase the speed of the horizontal scanning circuit as compared to the case where pixels for one row are driven during one horizontal scanning period.

However, as the speed of the horizontal scanning circuit increases, the circuit configuration becomes more difficult and power consumption increases.

Further, in this conventional technology, as described above, an A/D converter,
Since a digital double-speed conversion circuit consisting of a digital memory, a D/A converter, etc. is used, there is also the problem that the circuit scale becomes large.

On the other hand, in the latter proposed example, in order to realize the triangular color filter arrangement, image signals delayed by 1/2 period of the horizontal clock are used for each row to write to the liquid crystal panel. Furthermore, a dot sequential scanning method was used in which data was written one pixel at a time. Therefore, although it is effective in reducing the frequency of the horizontal clock, there is a problem that it is not always possible to take enough time to write to each pixel, and if two rows of pixels are selectively driven during one horizontal scanning period in order to perform high-definition display. The problem was that I couldn't tell.

That is, this prior art does not take into consideration the line sequential scanning method that allows sufficient writing time for each pixel, or high-definition display with as many as 480 vertical pixels.

Note that the line sequential scanning method means that data to be written to the liquid crystal element is stored in a storage means for one line, and then,
The purpose of the present invention is to solve the above-mentioned problems of the conventional technology, eliminate the need to speed up the circuit itself, and , a double-speed line that can selectively drive two or more rows of pixels during one horizontal scanning period without using a digital double-speed conversion circuit, and in addition, supports a triangular color filter arrangement using a line sequential scanning method. An object of the present invention is to provide a progressive scanning circuit.

[Means to solve the problem]

In order to achieve the above object, the present invention arranges a plurality of pixels consisting of switching elements and display elements in a matrix, connects the pixels in the same column to the same column signal electrode, and then connects the pixels in the same column to the same column signal electrode. It has a display means configured by rearranging pixels in odd rows and pixels in even rows so that they are shifted by a predetermined amount from each other in the row direction in the pixels connected to the signal electrode, and the switching element of each pixel is In an active matrix image display device that displays an image on the display means by applying a drive signal supplied to each column signal electrode to a display element of a desired pixel by on/off control, The first pixels have a time difference between the odd-numbered pixels and the even-numbered pixels according to the amount of shift in the row direction.
and a write timing signal generation means for generating a second write timing signal; four image signal storage means for respectively storing input image signals; and one horizontal scanning period of the input image signal from among these image signal storage means. each time, two different image signal storage means are selected, and the input image signal is written into one of the two selected image signal storage means based on the first write timing signal. , a writing means for writing the input image signal based on the second writing timing signal, and two image signal storage means other than the image signal storage means being written by the writing means into the other image signal storage means. , readout means for reading out the stored image signal in a time-division manner within one horizontal scanning period of the input image signal, respectively, are provided for each column signal electrode, and the image read out by each readout means. A signal is supplied to each corresponding column signal electrode as the drive signal.

[Effect]

In the display means, in order to form a triangular color filter arrangement,
Among pixels connected to the same column signal electrode, pixels in odd-numbered rows and pixels in even-numbered rows are arranged so as to be offset by a predetermined amount from each other in the row direction.

On the other hand, the writing means selects from among the four image signal storage means every horizontal scanning period of the input image signal.
selecting two different image signal storage means, ``writing the input image signal into one of the two selected image signal storage means based on the first writing timing signal; The input image signal is written into the image signal storage means based on the second write timing signal.

Here, the first write timing signal and the second write timing signal are configured to have a time difference from each other according to the amount of shift in the row direction between the pixels in the odd rows and the pixels in the even rows in the display means, The write timing signal is generated by the write timing signal generating means.

Therefore, the input image signals are written into the two selected image signal storage means, respectively, with a time difference corresponding to the amount of deviation.

The reading means reads the stored image signals from two image signal storage means other than the image signal storage means being written by the writing means within one horizontal scanning period of the input image signal. It is read out in divisions and supplied to the corresponding column signal electrodes as the drive signal.

As a result, from the two image signal storage means that are not currently being written, image signals having a time difference according to the amount of deviation are read out in a time-sharing manner two or more times within one horizontal scanning period, and the corresponding The signal will be supplied to the column signal electrode.

Therefore, according to the present invention, it is possible to selectively drive two or more rows of pixels during one horizontal scanning period using the line sequential scanning method while supporting the triangular color filter arrangement.

Therefore, sufficient writing time can be obtained for each pixel, and each pixel can be AC driven with a complete frame period (i.e., a frequency of 30 Hz), so flicker is reduced and the display is When a liquid crystal element is used as the element, high-definition display with 480 vertical pixels can be performed while extending the life of the liquid crystal element.

In addition, according to the present invention, there is no need to speed up the circuit itself, so there is no need to make the circuit configuration difficult or increase power consumption unlike in the past, and a digital double-speed conversion circuit is also used. Since this is not done, there is no need to say that the circuit scale will increase.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings, taking a liquid crystal element as an example of a display element.

FIG. 1 is a block diagram showing a double-speed line sequential scanning circuit for a triangular active matrix type liquid crystal image display device as a first embodiment of the present invention.

In FIG. 1, 1 is a horizontal scanning shift register, 8 is a latch circuit, WAc, W, is a selection switch, 3A,
3B, 3C, 3D are AND gates, S/H-A, S/H
-B, S/H-C, S/H-D are sample and hold circuits, 4 is an inverting amplifier, SA, 3m.

Sc, S11 are analog switches, 5 is a buffer amplifier, 6 is a thin film transistor (hereinafter referred to as TPT) liquid crystal panel, 7 is a shift register for vertical scanning, Drl, Dr
2. Dr3 is the column signal electrode of the TFT liquid crystal panel 6, Cal
, Ga2. Ga3. Ga4 and Ga5 are row signal electrodes of the TPT liquid crystal panel 6.

Further, FIG. 2 is a timing chart showing the timing of input/output signals of the horizontal scanning shift register, latch circuit, and selection switch in FIG. 1.

In addition, in FIG. 2, DHg shown at the bottom is a signal used in the embodiment of FIG. 1O, which will be described later.

A normal image signal is, for example, a point-sequential scanning signal, such as an NTSC image signal, which transmits the display contents at each point in the horizontal direction of the screen in time series.

However, since the operation speed of the TFT liquid crystal panel 6 is slow, in this embodiment, the display contents for one horizontal scanning period are temporarily held by the sample hold circuits S/H-A and S/H-B.
, S/H-C, and S/H-D, and then outputs one line at a time to drive the TFT liquid crystal panel 6, using a line sequential scanning method.

The horizontal scanning shift register 1 functions to generate sampling pulses for sampling and extracting signals necessary for driving each pixel from image signals inputted in time series.
As its control signal, the start pulse D Hl +
Shift clock φ□ is input. The frequency of the shift clock φ□ is determined by the number of display pixels in the row direction, and the horizontal scanning shift register l sequentially delays the start pulse DHI with the cycle of the shift clock φM+, and
+QI4iz rQH+x... Output as follows.

Here, since the TFT liquid crystal panel 6 has a triangular color filter arrangement, the positions of display pixels differ by 1.5 pixels for each row. Therefore, it is necessary to change the timing of the sampling pulse by 1.5 pixels for each row.

Therefore, using the latch circuit 8, each output QHIt + Q14 + s + QHI of the horizontal scanning shift register 1
4 +... Delay the phase by 0.5 pixel, QH
z□+ Qnz3rQHtar ...Output is obtained. At this time, the output QH! of the latch circuit 8 corresponds to the output Q Hl j of the horizontal scanning shift register 1. (j+
1. This means that the phase is delayed by 1.5 pixels. However, j=1.2, 3°, etc., and the same applies hereinafter.

Next, Fl is a frame period signal whose logic level is inverted every field. Using this Fl signal,
With selection switches WAc and W■, sample and hold circuit S
Sampling pulse QJAC input to /HA and S/H-C and sampling pulse QJID input manually to S/H-B and S/HD are selected.

That is, in the first field, the sampling pulse QjA
The output QMIj of the horizontal scanning shift register 1 is used as c, and the output QH! of the latch circuit 8 is used as the sampling pulse QJllD. +j+l), and conversely, in the second field, the output QH2(j+11) of the latch circuit 8 is selected as the sampling pulse QjAc, and the output Q)IIJ of the horizontal scanning shift register 1 is selected as the sampling pulse Q, go. select.

Since there is no difference in operation depending on each field, first,
The explanation will be continued below using the operation in a field as an example.

FIG. 3 is a timing chart showing the timing of the main signals and the operation of the sample and hold circuit in the first field in FIG.

In FIG. 3, W represents writing, R represents reading, and numbers in parentheses represent line numbers.

The selection signals H, , H2 are sampling pulses QJACI
Qjmo sample and hold circuit S/H-A, S/H-
This signal determines whether to supply the signal to B, S/H-C, or S/H-D.

As shown in Fig. 3, the signal H,,H, has a period of two horizontal scanning periods, and its logic level is inverted every horizontal scanning period. k
It will be abbreviated as H. ), then the sampling pulse Qj
Ac, QjlI! , are sent to sample and hold circuits S/H-A and S/H-B by AND gates 3A and 3B
As a + Q js, and in 2H, sampling pulses QjAc, QjlIIl are AND gates 3C, 3
Sample and hold circuit S/H-C, S/H-D by D
Q J CI Q JD, respectively.

On the other hand, the R, G, and B image signals V1deo are respectively input to the inverting amplifier 4, and each sample hold circuit has
Outputs R+, R-G+, G-, B+ of each inverting amplifier 4
, B- is input. Therefore, each sample hold circuit S/H-A, S/H-B, S/H-C,
S/H-D converts the output of the input inverting amplifier 4 into the previous sampling pulse Qj^+Q=m, QJCI
A write operation is performed by sampling and holding at the timing of Qjn.

In this embodiment, the TFT liquid crystal panel 6 has each column signal electrode D.
Since the configuration is such that pixels of the same color are connected to rj, four sample and hold circuits S/H-A, S/H-B, and S/H-C are provided for driving one column signal electrode. ，
Image signals of the same color are connected to the S/HD.

FIG. 4 is a waveform diagram showing input and output signal waveforms of the inverting amplifier in FIG. 1.

In FIG. 4, red is shown as an example, but the same applies to other colors. The inverting amplifier 4 amplifies the amplitude of the input image signal R as necessary and then inverts it to generate a signal symmetrical to the center voltage Vc as shown in FIG.
Two image signals R+ and R- of positive polarity and negative polarity are output.

Next, four sample and hold circuits S/H-AS/H-
The operations of B, S/H-C, and S/H-D will be described in more detail.

As mentioned earlier, in IH, the selection signal H1 selects the sample and hold circuits S/H-A and S/H-B to perform a write operation, and in 2H, the selection signal H2 selects the sample and hold circuits S/H-A and S/H-B. C, S/HD is selected and writing is performed.

On the other hand, analog switches Sa, Ss, Sc, and S.

As the control signals Ha, Hs, He, HD, the third
As shown in the figure, the period is 2 horizontal scanning periods and the duty is
If a four-phase signal with y) of 1/4 is used, in IH where write operation is performed in sample and hold circuits S/H-A and S/H-B, sample and hold circuits S/H-C and S/H-
D is sequentially selected by control signals He and Ho to perform a read operation. In addition, in 2H, the sample and hold circuit S/H-A is used conversely.

S/H-B is sequentially selected by control signals HA and H1 to perform a read operation. Sample hold circuit S/H-A
, S/H-C has a positive polarity signal R+.

G+, B+ are also sample and hold circuits S/H-B,
Since negative polarity signals R- and G-B- are written in S/H-D, these read operations result in polarity reversal for each column signal electrode Drj every 1/2 horizontal scanning period. The image signal is outputted via the buffer amplifier 5.

On the other hand, the vertical scanning shift register 7 receives a start pulse Dv and a shift clock φ as shown in FIG. Qvt+QV:l+”
'...' are row signal electrodes Gal, Ga2 . Ga3...
...is output. Then, at that time, the image signals outputted onto each column signal electrode Drj are written into the corresponding pixels.

Note that the sampling pulses input to the sample hold circuits S/H-B and S/H-D are Q, m, Q j
Since the phase of n is delayed by 1.5 pixels, the image signal can be correctly written to each pixel of the triangular filter arrangement.

FIG. 5 is a circuit diagram showing the configuration of each pixel of the TPT liquid crystal panel in FIG. 1.

In FIG. 5, IO is a TFT, and 11 is a liquid crystal cell.

Row signal electrode Gai from vertical scanning shift register 7
When a signal is input to (i=1.2, 3, . . .), TPTIO becomes conductive and the image signal on the column signal electrode Drj is applied to the liquid crystal cell 11. Here, liquid crystal cell 11
Opposite potential of ■,. , are fixed at a constant potential such that the liquid crystal cell 11 is driven symmetrically in positive and negative directions with alternating current.

Next, the operation in the second field will be explained.

FIG. 6 is a timing chart showing the timing of the main signals and the operation of the sample and hold circuit in the second field in FIG.

In FIG. 6, W represents writing, R represents reading,
Numbers in parentheses indicate line numbers.

The operation in the second field is almost the same as the operation in the first field shown in FIG. 3, but the operation of the vertical scanning shift register 7 is slightly different.

That is, in the second field, the operation of the vertical scanning shift register 7 is changed to 1/2 horizontal scanning using a start pulse Dv delayed by 1/2 horizontal scanning period as shown in FIG. It only delays the cycle.

This is done to drive each pixel with an image signal having a different polarity for each field. That is, in this embodiment, the polarity of the image signal input to each sample and hold circuit is fixed. As mentioned above, in the second field, by delaying the operation of the vertical scanning shift register 7 by 1/2 horizontal scanning period, in the second field,
Each pixel can be driven with an image signal having a polarity different from that of the first field.

FIG. 7 is an explanatory diagram showing the driving status of each row of the TPT liquid crystal panel in the embodiment of FIG. 1.

In FIG. 7, horizontal lines indicate each row of the TPT liquid crystal panel 6, and black circles on the horizontal lines indicate pixels. Also, the numbers on the left side indicate the line number of each line. In addition, A to D are sample and hold circuits S/H-A, S/H-B, and S/H-, respectively.
A sample and hold circuit corresponding to C, S/HD and storing image signals for driving each row is shown. Furthermore, the symbols "-" and "-" indicate the polarity of the image signal that drives each row.

In FIG. 7, A to D and + on the left side.

shows the driving situation in the first field, and A on the right side shows the driving situation in the first field.
-D, +, and - indicate the driving situation in the second field.

Incidentally, the above also applies to FIGS. 9 and 11, which will be described later.

As described above, in order to perform high-definition display with 480 vertical pixels using an NTSC image signal, it is necessary to drive two rows of pixels during one horizontal scanning period due to flicker. Furthermore, in order to faithfully reproduce the ink-lace image signal, it is necessary to shift the combination of pixels for two rows driven during the horizontal scanning period for each field.

Furthermore, in order to drive the liquid crystal element with alternating current, it is necessary to drive each pixel with an image signal of a different polarity for each field. Furthermore, in order to prevent a difference in brightness between the upper and lower parts of the display screen, the polarity of the image signal that drives each pixel (i.e., the image signal applied to each column signal electrode) must be changed for each row. It is necessary to perform line-by-line polarity inversion driving to invert the polarity every 1/2 horizontal scanning period (that is, every 1/2 horizontal scanning period).

In order to satisfy all of the above conditions, in this example,
The drive system shown in FIG. 7 is used.

That is, the polarity of the image signal input to each sample-and-hold circuit is constant, and the sampling timing of each sample-and-hold circuit differs by 1.5 pixels from field to field. Further, the operating phase of the vertical scanning shift register 7 also differs from field to field by 1/2 horizontal scanning period.

As explained above, according to this embodiment, it is possible to perform high-definition display with 480 vertical pixels with less flicker and less deterioration in resolution, and to faithfully reproduce ink-lace image signals. Can be done. In addition, AC driving of the liquid crystal element can be performed perfectly, and since the polarity of the image signal that drives each pixel is different for each row, there is no difference in brightness across the entire display screen.

By the way, in the embodiment shown in FIG. 1 described above, the input signal is NT
This circuit is limited to cases where the input signal is an ink-lace image signal such as an SC system image signal, and is not applicable when the input signal is a non-interlace image signal for a personal computer display.

Therefore, next, an embodiment corresponding to the case where the input signal is a non-interlaced image signal will be described.

FIG. 8 is a block diagram showing a double-speed line sequential scanning circuit for a triangular active matrix type liquid crystal image display device as a second embodiment of the present invention.

This embodiment has a selection switch WAc for switching sampling pulses, compared to the embodiment shown in FIG.

The selection switch 5R115R11SGl+SG! which inverts the polarity of the image signal applied to each sample and hold circuit for each field. + Sl
There is no difference in configuration other than the addition of l+S and z. However, it is not necessary to shift the phase of the start pulse Dv of the vertical scanning shift register 7 by 1/2 horizontal scanning period for each field.

The detailed explanation of the operation in this embodiment is omitted because it is the same as that in the embodiment shown in FIG.

FIG. 9 is an explanatory diagram showing the driving status of each row of the TPT liquid crystal panel in the embodiment of FIG. 8.

In this embodiment, the combination of two lines driven during one horizontal scanning period is always constant regardless of the field, and the phase of the sampling pulse input to each sample and hold circuit is also always constant regardless of the field. . In addition, in order to perform AC drive and polarity inversion drive for each line of the liquid crystal element, it is necessary to drive each pixel with an image signal of a different polarity for each field, so a switch is used to select the polarity of the image signal input to each sample and hold circuit. S□+ 5R115G
Each field is inverted using IISGI Sm+ and Sag.

FIG. 10 is a block diagram showing a double-speed line sequential scanning circuit for a triangular active matrix type liquid crystal image display device as a third embodiment of the present invention.

The difference between this embodiment and the embodiment shown in FIG. 1 is that the latch circuit 8
0 instead, it is equipped with a horizontal scanning shift register 2 and employs field-by-field polarity reversal driving in which the polarity of the image signal that drives each pixel is made equal within the same field and reversed for each field. be.

In this embodiment, the clock φ given to the latch circuit 8 in the embodiment of FIG. 1 is used as the shift clock of the horizontal scanning shift register 2. The same signal as the start pulse D, l! shown at the bottom of FIG. 2 is also used as the start pulse.
If , respectively, are used, the outputs of the horizontal scanning shift register 2 will be QHz + QM□, Qi, 4, which are exactly the same as the output of the latch circuit 8 in FIG.・
... can be obtained. In addition, start pulse D
, Ql of the horizontal scanning shift register 1
II! You can also use the output.

FIG. 11 is an explanatory diagram showing the driving status of each row of the TPT liquid crystal panel in the embodiment of FIG. 10.

As far as FIG. 11 and FIG. 7 are compared, this embodiment differs from the embodiment shown in FIG. 1 only in the polarity of the image signal, and in this embodiment, all the samples in the first field are A positive polarity image signal is input to the hold circuit, and a negative polarity image signal is input to all sample and hold circuits in the second field. In this embodiment, this operation is performed using changeover switches S* and Sa in FIG. 1O.
, Ss is used.

According to this embodiment, an image signal (i.e.,
The polarity of the image signal applied to each column signal electrode is changed for each row (
That is, since it is not necessary to switch at every 1/2 horizontal scanning period, there is an advantage that the power consumption required for this is small.

Incidentally, in an actual image display device, the input image signal can have both inklace and non-interlace specifications, and therefore, a double-speed line sequential scanning circuit used in such an image display device can use both of these specifications. It is desirable to have a circuit that automatically corresponds to the specifications.

Therefore, next, an embodiment will be described which is compatible with both cases where the input signal is an interlaced image signal and a non-interlaced image signal.

FIG. 12 is a configuration diagram showing a double-speed line sequential scanning circuit for a triangular active matrix type liquid crystal image display device as a fourth embodiment of the present invention.

Comparing the embodiment shown in FIG. 1 and the embodiment shown in FIG. 8, the only difference between the two is the timing of the sampling pulse applied to each sample-and-hold circuit and the way the polarity of the image signal is applied. be.

Therefore, in this embodiment, the selection switches SR1, SE2+ SGI+ used in the embodiment of FIG. 8 are added to the embodiment of FIG.
Set, S□l smz are added to make it compatible with both interlaced and non-interlaced image signals.

In this embodiment, the discrimination signal INT is a signal indicating whether the input signal is an interlaced image signal or a non-interlaced image signal, and is connected to the AND gates 20 and 21.
And the inverter gate 22 selects the Fl signal when the image signal is an ink-lace image signal.
IID, and when it is a non-interlaced image signal, select switch 5IIl+ Sll SGl+
Sc! r S□+Sl! supply to. Other operations are completely the same as those in the embodiments shown in FIGS. 1 and 8, and will therefore be omitted.

FIG. 13 is a configuration diagram showing a double-speed line sequential scanning circuit for a triangular active matrix type liquid crystal image display device as a fifth embodiment of the present invention.

The difference between this embodiment and the embodiment shown in FIG. 12 is that the sampling pulse generation means composed of a horizontal scanning shift register 1 and a latch circuit 8 is replaced with one horizontal scanning shift register 10. be.

In this embodiment, the shift clock φ of the horizontal scanning shift register 10. is a signal having twice the frequency of the shift clock φ1 of the horizontal scanning shift register 1 shown in FIG. Other operations are exactly the same as the embodiment shown in FIG. 12.

FIG. 14 is a configuration diagram showing a double-speed line sequential scanning circuit for a triangular active matrix type liquid crystal image display device as a sixth embodiment of the present invention.

In each of the embodiments described above, a TFT liquid crystal panel 6 with the same color connection in which pixels of the same color are connected to one column signal electrode is used as the TPT liquid crystal pulse, whereas in this embodiment, , a TFT liquid crystal panel 60 with different color connections is used, in which pixels of two different colors are connected to one column signal electrode in each row.

The difference between this embodiment and the embodiment shown in FIG.
There are two other differences in addition to the structure of the PT liquid crystal panel.

First, the first difference is that four sample and hold circuits are provided per column signal electrode, S/H-A, S/H-B, and S/H.
- Sample and hold circuit S/H-A, S/H-
C and the sample and hold circuit S/H-B, S/) (-D) are different.In other words, this means that the color of the pixels connected to one column signal electrode is changed every row. It is tailored to different people.

Next, the second difference is the selection switches WAc, W,.

In each of the embodiments described above, the phases of the two sampling pulses to be selected are shifted by 1.5 pixels from each other, for example, QHII and Q, and It□. □ Both are 0. like 2I.
This point is shifted by 5 pixels. This is also just to accommodate the fact that the positions of pixels of different colors connected to one column signal electrode are shifted by 0.5 pixel.

Other operations are completely similar to the embodiment shown in FIG.

In this embodiment, in the configuration of the embodiment shown in FIG. 13, instead of the TFT liquid crystal panel 6 connected with the same color, TFTs with different colors
Although the liquid crystal panel 60 is used, it goes without saying that the sample and hold circuits are also used in the embodiments shown in FIGS. By simply changing the color of the input image signal and the phase of the sampling pulse, it is possible to use TFT liquid crystal panels 60 with different color connections instead of the TFT liquid crystal panels 6 with same color connections.

Each of the embodiments has been explained using a liquid crystal element as an example of the display element, but in the case of an active matrix image display device, other display elements such as EL (electroluminescence) or fluorescent display tubes may be used. Even if you use
It is clear that similar effects can be obtained with similar configurations.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to selectively drive two or more rows of pixels during one horizontal scanning period using the line sequential scanning method while supporting the triangular color filter arrangement.

Therefore, sufficient writing time can be obtained for each pixel, and each pixel can be written completely over the frame period (i.e.,
Since it can be driven with AC at a frequency of 307, there is less flicker.Furthermore, when a liquid crystal element is used as the display element, the lifespan of the liquid crystal element can be extended while the number of vertical pixels is 48.
High-definition display of 0 pixels can be performed.

Furthermore, according to this paper, it is possible to make the input signal compatible with both ink-laced and non-interlaced image signals. It is also possible to perform polarity reversal driving every time.

Furthermore, when the input signal is an ink-lace image signal, the display element is not limited to a liquid crystal element, but by changing the combination of pixels for two rows driven during one horizontal scanning period for each field. This has the effect of improving the vertical resolution of the screen.

Furthermore, according to the present invention, there is no need to increase the speed of the circuit itself, so there is no need to make the circuit configuration difficult or increase power consumption unlike in the past. Since it is not used, the circuit scale does not increase.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart showing the timing of input and output signals of the horizontal scanning shift register, latch circuit, and selection switch in FIG. 1, and FIG. 1 is a timing chart showing the main signals in the first field and the operation timing of the sample-and-hold circuit in FIG. 1. FIG. FIG. 1 is a circuit diagram showing the configuration of each pixel of the TPT liquid crystal panel, FIG. 6 is a timing chart showing the main signals in the second field in FIG. 1 and the operation timing of the sample and hold circuit, and FIG. FIG. 8 is an explanatory diagram showing the driving status of each row of the TPT liquid crystal panel in the embodiment of FIG. 1, FIG. 8 is a configuration diagram showing the second embodiment of the present invention, and FIG. 9 is a TPT liquid crystal panel in the embodiment of FIG. An explanatory diagram showing the driving status of each row of the panel, FIG. 10 is a configuration diagram showing the third embodiment of the present invention, and FIG. 11 is a T in the embodiment of FIG. 10.
Explanatory diagram showing the driving status of each row of the PT liquid crystal panel, No. 12
FIG. 13 is a block diagram showing a fourth embodiment of the present invention, FIG. 13 is a block diagram showing a fifth embodiment of the present invention, and FIG. 14 is a block diagram showing a sixth embodiment of the present invention. be. Explanation of symbols 1.2.10...Horizontal scanning shift register, 3A,
3B, 3C, 3D...AND gate, 4...Inverting amplifier, 5...Buffer amplifier, 6.60...TPT
Liquid crystal panel, 7... Vertical scanning shift register, 8.
...Latch circuit, w, c, Wl. ...Selection switch, S/H-A, S/H-B, S/H-C, S/I(-D
...Sample and hold circuit. Agent Patent Attorney Akio Namiki 11121! ! W3 Figure I! 4 Illustration Lecture 5 Illustration Hisho Cell Figure 6

Claims (1)

[Claims] 1. A plurality of pixels each consisting of a switching element and a display element are arranged in a matrix, and the pixels in the same column are connected to the same column signal electrode, and then connected to the same column signal electrode. The display device includes display means configured by rearranging pixels in odd-numbered rows and pixels in even-numbered rows so that they are shifted by a predetermined amount from each other in the row direction, and controls on/off of a switching element of each pixel. By applying the drive signal supplied to each column signal electrode to the display element of a desired pixel,
In an active matrix type image display device that displays an image on the display means, first pixels having a time difference between odd-numbered row pixels and even-numbered row pixels in the display means according to the amount of shift in the row direction;
and write timing signal generation means for generating a second write timing signal; four image signal storage means for respectively storing input image signals; and one horizontal scanning period of the input image signal from among these image signal storage means. each time, two different image signal storage means are selected, and the input image signal is written into one of the two selected image signal storage means based on the first write timing signal. , a writing means for writing the input image signal into the other image signal storage means based on the second write timing signal, and a writing means for writing the input image signal from two image signal storage means other than the image signal storage means being written by the writing means. , respectively, readout means for reading out stored image signals in a time-division manner within one horizontal scanning period of the input image signal; and are provided for each column signal electrode, respectively, and the image read out by each readout means. A double-speed line sequential scanning circuit characterized in that a signal is supplied to each corresponding column signal electrode as the drive signal. 2. In the double-speed line sequential scanning circuit according to claim 1, the write timing signal generating means provided for each column signal electrode generates a plurality of signals having mutually different timings, and transmits each signal to each column. a first shift register that outputs the first write timing signal to the write means provided for each signal electrode; a second shift register that outputs the second write timing signal to the write means provided in the double-speed line sequential scanning circuit. 3. In the double-speed linear sequential scanning circuit according to claim 2, the first shift register (or the second shift register) is replaced with the second shift register (or the first shift register).
A plurality of signals generated in the second shift register) are delayed, and each signal obtained by the delay is sent to the second writing means provided for each column signal electrode.
1. A double-speed line sequential scanning circuit comprising a delay means for outputting a write timing signal (or a first write timing signal). 4. In the double-speed line sequential scanning circuit according to claim 2, a plurality of signals having mutually different timings are generated in place of the first and second shift registers, and some of these signals are A third shift register is provided which outputs the first write timing signal to the write means provided for each column signal electrode, and outputs the remaining signal as the second write timing signal. Double-speed linear sequential scanning circuit. 5. In the double-speed line sequential scanning circuit according to claim 1, 2, 3, or 4, the reading means selects the image signal storage means from among the two image signal storage means other than the image signal storage means being written by the writing means. When the input image signal is in an odd field period (or even field period), an image to which the input image signal is first written based on the first writing timing signal within one horizontal scanning period of the input image signal. Reading the stored image signal from the signal storage means, and then reading the stored image signal from the image signal storage means into which the input image signal has been written based on the second write timing signal, When the input image signal is in an even field period (or an odd field period), an image written with the input image signal is first written with the second writing timing signal within one horizontal scanning period of the input image signal. The stored image signal is read from the signal storage means, and then the stored image signal is read from the image signal storage means into which the input image signal has been written in response to the first write timing signal. A double-speed line sequential scanning circuit characterized by: 6. The double-speed line sequential scanning circuit according to claim 5, further comprising determining means for determining whether the input image signal is an interlaced signal or a non-interlaced signal, the determining means comprising: When determining that the input image signal is a non-interlaced signal, the reading means reads one of the input image signals out of two image signal storage means other than the image signal storage means being written by the writing means. Within a horizontal scanning period, first reading a stored image signal from an image signal storage means into which an input image signal has been written based on the first write timing signal (or second write timing signal);
Next, the second write timing signal (or the first
1. A double-speed line sequential scanning circuit, characterized in that a stored image signal is read out from an image signal storage means into which an input image signal has been written based on a write timing signal (write timing signal). 7. In the double-speed line sequential scanning circuit according to claim 1, 2, 3, 4, 5, or 6, the amount of deviation in the row direction between the odd-numbered row pixels and the even-numbered pixels in the display means is 1. 5
The deviation is equivalent to a pixel, and the time difference between the first write timing signal and the second write timing signal generated by the write timing signal generating means provided for each column signal electrode is 1.5 pixels. A double-speed line sequential scanning circuit characterized by a considerable time difference. 8. In the double-speed line sequential scanning circuit according to claim 1, 2, 3, 4, 5, or 6, the amount of deviation in the row direction between the odd-numbered pixels and the even-numbered pixels in the display means is 0. 5
The deviation is equivalent to a pixel, and the time difference between the first write timing signal and the second write timing signal generated by the write timing signal generating means provided for each column signal electrode is 0.5 pixel. A double-speed line sequential scanning circuit characterized by a considerable time difference. 9. The double-speed line sequential scanning circuit according to claim 1, 2, 3, 4, 5, 6, 7, or 8, wherein the active matrix type image display device is used as an image display section of a television receiver. A double-speed linear sequential scanning circuit. 10. The double-speed linear sequential scanning circuit according to claim 1, 2, 3, 4, 5, 6, 7, or 8, wherein the active matrix type image display device is used as a monitor display for a computer or the like. Double-speed linear sequential scanning circuit. 11. The double-speed line sequential scanning circuit according to claim 1, 2, 3, 4, 5, 6, 7, or 8, wherein the active matrix type image display device is used as an electroview finder of a camera. Double-speed linear sequential scanning circuit.