JPH0281445A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To facilitate high density mount of integrated circuit semiconductor chips by a method wherein the semiconductor chips are mounted in multilayer arrangement and the respective semiconductor chips are electrically connected to each other through through-holes formed in a plate held between the semiconductor chips. CONSTITUTION:Semiconductor chips 2 and 3 are die-bonded to both the surfaces 1a and 1b of a base plate 1 composed of a metal plate and other parts of the base plate surfaces are covered with SiO2 insulating films 20. A lead plate 6 and a lead plate 7 are connected to the bonding pads 2a of the chip 2 and the bonding pads 3a of the chip 3 respectively by intermetallic joint. The lead plates 6 and 7 are electrically connected to each other through conductive plugs 8 buried in through-holes 1c formed in the base plate 1. The SiO2 insulating films 20 are formed also on the inside surface of the through-holes 1c of the base plate 1 in which the conductive plugs 8 are buried to insulate the conductive plugs 8 from the base plate 1. With this constitution, the electrical connection between the bonding pads 2a and 3a of the semiconductor chips 2 and 3 can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly relates to a semiconductor device in which a plurality of integrated circuit semiconductor chips are mounted in multiple layers.

[Prior art]

In recent years, semiconductor integrated circuits have become highly integrated and integrated into one chip. This is because when semiconductor elements containing semiconductor chips are mounted on a printed wiring board and used in combination with each other, the electrical connection lines between them become long.
This was done in consideration of the fact that a delay would occur in signal transmission and that the overall size of the device would increase. Therefore, 1
Consideration is being given to increasing the size of a single semiconductor chip so that more integrated circuits can be packed into one chip.

Furthermore, a hybrid integrated circuit device is known in which circuit elements are mounted on both sides of a ceramic substrate to achieve high-density mounting of the circuit elements.

[Problem to be solved by the invention]

However, when the chip size of a semiconductor chip is increased, the manufacturing yield is extremely reduced, and the price of a semiconductor device mounted with such a semiconductor chip becomes high.

Furthermore, the hybrid integrated circuit device described above has problems in terms of higher functionality, higher performance, smaller size, lower cost, and mass productivity than semiconductor integrated circuit chips.

Therefore, there is a need for a semiconductor device that is small, can mount many integrated circuits, is inexpensive, and can shorten the length of signal lines.

SUMMARY OF THE INVENTION An object of the present invention is to achieve the above-mentioned problems and to provide a semiconductor device that is small in size, can mount many integrated circuits, and can have short signal lines.

[Means to solve the problem]

The semiconductor device of the present invention includes a base plate and a semiconductor chip which is sandwiched between the base plate and die-bonded to both sides of the base plate, and the electrical connection between the bonding pads of the semiconductor chip is made through a through hole provided in the base plate. It is characterized by being carried out through a hole.

[Effect]

In the semiconductor device of the present invention, semiconductor chips for integrated circuits are mounted in multiple layers, and electrical connections between the semiconductor chips are made through through holes formed in a plate sandwiched between them. enables high-density packaging.

〔Example〕

Embodiments according to the present invention will be described below with reference to the drawings.

Elements with the same reference numerals have the same functions, so duplicate explanations will be omitted.

1 is a partially exploded perspective view of a semiconductor device according to the present invention, FIG. 3 is a top view thereof, and FIG. 2 is a sectional view taken along line A--A in FIG. 3. As shown in these figures, in the semiconductor device of the embodiment according to the present invention, semiconductor chips 2.3 are die-bonded on both surfaces 1a and lb of the base plate 1, respectively. This base plate 1 is a metal plate, and a portion other than the region where the semiconductor chip 2.3 is die-bonded is covered with an insulating film 20 of 5i02. Then, this base plate is inserted into the recess 4a in the semiconductor device package 4, and the base plate is inserted into the recess 4a in the semiconductor device package 4.
It is supported on an edge portion 4b extending from the periphery of. On the bonding pad 2a of the semiconductor chip 2 that is electrically connected to the bonding pad 3a of the semiconductor chip 3,
The lead plate 6 is pre-bonded. In the present invention, the lead plate 6 and the bonding pads 2a of the semiconductor chip 2 are connected using metal-to-metal bonding. Furthermore, one lead plate 7 is similarly connected to the bonding pad 3a of the semiconductor chip 3 die-bonded to the lower surface 1b of the base plate 1. These lead plates 6.7 are electrically connected via a conductive frame 8 embedded in a through hole IC formed in the base plate 1. This conductive frame 8 and lead plate 6.
7 is also connected using the connection method described above. Incidentally, an insulating film 20 of 5i02 is also formed on the inner surface of the through hole IC of the base plate in which the conductive frame 8 is embedded, to insulate the base plate 1 and the conductive frame 8. In this way, the bonding pads 2a of the semiconductor chip 2 and the bonding pads 3a of the semiconductor chip 3 are electrically connected.

On the other hand, leads 9 are provided around the recess 4a of the semiconductor device package 4 for transmitting and extracting signals to and from the integrated circuit of the semiconductor chip 2.3, and for supplying power.

This lead 9 is electrically connected to an external terminal (not shown).

The bonding pads 2b and 2c of the semiconductor chip 2.3 connected to this lead 9 are connected to the lead plate 1, respectively.
0.11 are connected by the above-described joining method, and each of these lead plates 10.11 is electrically connected to both sides of the lead 9 by the so-called bump method.

Further, the lead plates 10.11 are respectively connected to the conductive portions 1f formed on the edge portion 1e by the above connection method. In this way, electrical connection between the semiconductor chip 2.3 and the external terminals is achieved.

Since the base plate 1 is made of a metal material, it has good thermal conductivity and also functions as a heat sink. Each lead plate must be precisely positioned in order to accurately connect them to each other. Therefore, these lead plates were attached to a film carrier and the so-called TAB method (Ta
By applying pe Automate Bonding), positioning and electrical connections can be easily made.

The present invention is not limited to the above embodiments, and various modifications may be made.

Specifically, in the above embodiment, the bump method is used to connect the leads of the semiconductor device package and the lead plate, but the method is not limited to this method. For example, the metal-to-metal bonding method described earlier may be used. You may use it.

Furthermore, although the above embodiment describes an example in which one semiconductor chip is die-bonded to one side of the base plate, a plurality of semiconductor chips may be die-bonded and electrically connected to each other. .

〔Effect of the invention〕

As described above, in the semiconductor device of the present invention, since semiconductor chips are mounted in multiple layers, the semiconductor device can be made smaller, more highly functional, and lower in cost.

Furthermore, since multiple semiconductor chips can be mounted in this way,
It is effective to combine semiconductor chips with integrated circuits with different functions, such as gate array elements and standard cells, or to mount a semiconductor chip with an EFROM on the upper side and a logic circuit on the lower side.

[Brief explanation of the drawing]

FIG. 1 is a partially exploded perspective view of a semiconductor device according to the present invention;
2 is a sectional view of the semiconductor device shown in FIG. 1, and FIG. 3 is a top view of the semiconductor device shown in FIG. 1. 1...Base plate, 2.3...Semiconductor chip,
2a, 2b, 3a, 3b... bonding pad, 4
. . . Package for semiconductor device, 4a . . . Recessed portion, 6.
7.10.11...Reed plate, 9...Reed. Patent applicant: Sumitomo Electric Industries, Ltd. Representative patent attorney Yoshiki Hase
Fumiaki Terasaki Figure 1

Claims (1)

[Claims] 1. A semiconductor chip sandwiching the base plate and die-bonded to both sides of the base plate, the electrical connection between the bonding pads of the semiconductor chip being provided on the base plate. A semiconductor device that is made through a through hole. 2. The semiconductor device according to claim 1, wherein the base plate is placed in a package to which a lead frame is attached, and the electrical connection between the electrical terminal of the lead frame and the bonding pad of the semiconductor chip is made by a bump method. .