JPH0277934A - Line buffer memory - Google Patents

Abstract

PURPOSE:To perform both reading and writing actions at one time and to improve the time conversion efficiency by preparing two memory areas having the toggle actions and switching the memory actions via a write register, a read counter, a comparator, etc. CONSTITUTION:A RAM(A) 6 and a RAM(B) 7 are provided and the RAM 7(6) is set in a read state when the RAM 6(7) is kept in a write state. A write register 10 latches the final write address and this address is compared with the counted value of a read counter 9 kept in a read state by a comparator 11. When the coincidence of this comparison is obtained, an interruption signal 3 is generated and a toggle signal is requested to a controller. Thus the controller generates a toggle signal 20. Then a toggle action is carried out and the memory actions are switched between the RAM 6 and the RAM 7. As a result, the data is never destroyed despite the simultaneous performance of both reading and writing actions. Thus it is possible to perform both reading and writing actions at one time and to the time conversion efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line buffer memory for efficiently performing time conversion (frequency A - frequency B) of data.

[Conventional technology]

Figure 3 shows a conventional device that performs time conversion of data, which is necessary when displaying an image created by a microcomputer (hereinafter referred to as microcomputer) on an image display device at a constant rhythm. This is a diagram showing an example of a configuration, and shows what is called a dual-baud RAM.In the diagram, 1 is an input terminal to which an input signal is connected, and 2 is a time-converted output signal. Output terminal 4 is a write clock (for example, the CPU of a microcomputer, M
A terminal 5 is a terminal for applying a read clock (a ride clock of a controller such as a PU), and a terminal 5 is a terminal for applying a read clock that is a rhythm required after conversion (for example, a rhythm of an image display device that is a peripheral device of the microcomputer). Also, Figure 4 shows the 3rd
FIG. 2 is a timing diagram for explaining the operation of the device shown in FIG.
100 is data stored in the RAM 16.

Next, the operation of the apparatus shown in FIG. 3 will be described in the case where data generated at a frequency of 1 kHz, for example, is converted to 2 kHz.

First, as shown in FIG. 4(a), when a 1 kHz write clock is applied to the write clock input terminal 4 and write data is applied to the input terminal 1, data is sequentially written from address 0 of the RAM 16 in synchronization with a 1 kHz cycle. Write data is stored. The figure shows an example in which 4-bit data "0110" is stored from address 0 to address 3.

On the other hand, as shown in FIG. 4(b), at the time of reading, 2kHz
When a read clock of Data “011
An example is shown in which 0'' are read out in order.

[Problem to be solved by the invention]

Conventional devices that perform time conversion of data are configured as described above, so if writing is performed at the same time as reading, there is a risk of destroying the data being read. Write-)
There is a problem that the efficiency of time conversion deteriorates because reading and writing cannot be performed at the same time.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a line buffer memory that can perform reading and writing simultaneously and can perform time conversion efficiently.

[Means to solve the problem]

The line buffer memory according to the present invention is A.

B uses two memory areas and adopts a toggle method in which when A (B) is in the write state, B (A) is in the read state,
Switching of two memory operations (A (B) is in the read state from the write state M, B (A) is in the read state and latches the final write address in the register, and the memory B (A) is in the read state The read counter value of is compared with the value latched in the register, and when they match,
It is designed to generate an interrupt signal to request a toggle signal.

[Effect]

In this invention, two memory areas A and B are used,
When A (B) is in the write state, B (A) is set to be in the read state, the timing for the toggle operation is obtained internally from the write address, and when that timing is reached, an interrupt is issued to the controller such as the CPU or MPU. By generating a signal to notify a controller such as a CPU or MPU of the timing of toggle operation, the controller generates a toggle signal and performs the toggle operation, making it possible to perform reading and writing at the same time.

〔Example〕

FIG. 1 is a configuration diagram showing a line buffer memory according to an embodiment of the present invention. In the figure, 1 is an input terminal to which an input signal is connected, 2 is an output terminal to which a time-converted output signal is output, and 3 is an output terminal to which a time-converted output signal is output. is CPU.

An interrupt terminal outputs an interrupt signal to request a toggle signal from a controller such as an MPU, and 4 is a write clock (for example, a microcomputer CPU, MPU 5 is a terminal that applies a read clock that becomes the rhythm required after conversion (for example, the rhythm of an image display device that is a peripheral device of the microcomputer), and 6 is a terminal that applies a read clock that is the rhythm of an image display device that is a peripheral device of the above-mentioned microcomputer. ), 7 is RAM
(B), 8 is a write counter that indicates the RAM address when writing, 9 is a read counter that indicates the RAM address when reading, and 10 holds the final write address during toggle (when switching between two memory operations). Write register, 11 is a comparator that compares the values of read counter 9 and write register 10 and generates an interrupt signal when they match, 12 is input signal 1 to RAM (A) 6 or RAM
(B) Selector that distributes write clock 4 or read clock 5 to RAM (A) 6 or RAM
CB) selector to allocate to 7, 14 is RAM (A
) 6 or RAM (B) 7, and 20 is a toggle terminal to which a toggle signal is applied to change the state of the RAM.

2 is a timing chart for explaining the operation of the device shown in FIG. 1, and 101 and 102 are RAMs, respectively.
This is the data stored in (A) and (B). In this figure, for simplicity, RAM (A) is used.

In (B), the number of bits for writing or reading is 4 bits, and the clock frequency for writing and reading is the same.

First, RAM (A) is set to the write state, and the information “0110” input to input terminal 1 is written to addresses 0 to 3 of RAM (A) in synchronization with write clock 4 (second Figure (a)). At that time, RAM (B) is set to the read state, and the RAM (B) is read out in synchronization with the read clock 5.
The information written in addresses 0 to 3 of (B) “10
01" is output to the output terminal 2. At this time, 3" at address 3 is latched in the write register 10, and when the read counter 9 selects "3" at address 3, the comparator 11 outputs an interrupt signal. 3 and requests a toggle signal from a controller such as a CPU or MPU. In response, the controller generates a toggle signal 20 ((b) in the same figure).
. This toggle signal 20 causes RAM (A), (B
) is switched (toggled), but at that time, the write register 10 is loaded with the last address 3 of the data written in RAM (A).

The toggle signal 20 puts the RAM (A) into a read state, and the information "0110" previously written at addresses 0 to 3 of the RAM (A) is output to the output terminal 2 in synchronization with the read clock 5. At this time, "3" is latched in the write register 10 as described above, and when the read counter 9 selects address 3, 3', interrupt signal 3 is generated in the same way as before ((C) )). In addition, RAM (B
) is in the write state at that time, in this example “0011”
information is written ((d) in the same figure).

In such a device, there is no risk of data destruction even when reading and writing are performed simultaneously, and time conversion can be performed efficiently.

Note that in the above embodiment, RAM (A>, RAM (B)
has been explained as a data memory area with a width of 1 bit each, but this is a data memory area with a width of multiple bits (for example, I BYTE = 8b
It may be a data memory area of .it), and these may be dynamic RAM or static RAM.

Further, in the above embodiment, the write clock 4 and the read clock 5 have the same frequency, but these clocks can be freely selected, and whichever clock is faster can be used without problems.

〔Effect of the invention〕

As described above, according to the line buffer memory according to the present invention, the two memories have a toggle configuration, the timing for toggling operation is obtained from the write address, and when the timing comes, an interrupt is generated to request a toggle signal from the controller. Since the signal is generated, time conversion can be performed efficiently.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a line buffer memory according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining its operation, FIG. 3 is a configuration diagram showing a conventional dual port RAM, and FIG. 4 is a timing diagram for explaining the operation. 3 is an interrupt terminal, 4 is a write clock terminal, 5 is a read clock terminal, 6 is a RAM (A), 7 is a RAM (
B), 10 is a write register, 11 is a comparator, 2
0 is a toggle terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a line buffer memory that performs time conversion of data, there are two memory areas where one is set to a write state and the other is set to a read state, and the final write address is set when the state of the two memory areas is switched. When the register for latching matches the read counter value of the memory area in the read state and the value latched in the above register, an interrupt signal is generated to request a toggle signal for performing the above switching. A line buffer memory characterized by comprising means.