JPH0273291A - Timing signal generating device - Google Patents

Abstract

PURPOSE:To generate a desired signal by providing a clock generator and reading out a desired timing signal written in advance in a ROM synchronously with a counter. CONSTITUTION:When a clock generator 1 outputs a clock, a counter 2 operates synchronously with the clock. The counter 2 is connected to address terminals 31, 38 of a ROM 3, and write data of the ROM 3 is outputted successively by synchronizing with an operation of the counter 2. In this cased, a desired timing signal is applied to each data bit of the ROM 3, and timing data is written in the ROM 3 in advance. When the generator 1 outputs the clock, the counter 2 operates. By synchronizing with this operation, the data of the ROM 3 is read out, and the desired timing signal can be generated easily. Also, by changing the storage contents of the ROM 3, the timing signal can be changed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timing signal generating device used in an information display device or the like using one light emitting diode.

(Prior Art) Conventionally, this type of timing signal generation device is composed of various logic integrated circuits (hereinafter referred to as logic ICs) such as an AND circuit, an OR circuit, a NOT circuit, a flip-flop, and a counter. It was configured so that a desired timing signal could be generated by a circuit that was a combination of ICs.

(Problems to be Solved by the Invention) However, in the conventional timing signal generator described above, when the timing signal generated becomes complex, the combination of logic ICs that constitute the circuit becomes complex, and it takes time to design one circuit. was there.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent timing signal generation device that can easily generate timing signals.

(Means for Solving the Problem) In order to achieve the above object, the present invention includes a ROM, a counter for reading data written in the ROM, and a clock generator for operating the counter. It is.

(Function) Therefore, according to the present invention, a desired timing signal is written in the ROM in advance as data, and the value of a counter operated by a clock output from a clock generator is used to specify the read address of the data. For example, since the ROM can sequentially read the written data, it is possible to easily generate a desired timing signal.

(Embodiment) FIG. 1 shows the configuration of one embodiment of the present invention. In FIG. 1, 1 is a clock generator, 2 is a counter, and 3 is a clock generator.
is a ROM, which outputs timing signals to data output terminals 311 to 318 using the output of counter 2 for address designation.

Next, the operation of the above embodiment will be explained. In the above embodiment, when the clock generator 1 outputs a clock, the counter 2 generates ll+ in synchronization with this clock. The output of counter 2 is the address terminal 31 to 38 of ROM3.
Since the ROM is connected to the ROM, if the ROM is kept in an output-enabled state at all times, the data written in the ROM will be sequentially output in synchronization with the operation of the counter. FIG. 2 is a diagram showing ROM write data and corresponding timing signals in one embodiment of the present invention. As shown in FIG. 2(a), a desired timing signal is applied to each data bit of the ROM 3. That is, when the timing signal is at a high level, the data bit for the timing signal is
When r 1 ++ is closed, it is set to "0" when it is at low level.

The timing signal data created in this way is
Write it in OM.

If this is read out continuously, the timing signal shown in FIG. 2(b) can be obtained. In this way, when the clock generator 1 outputs a clock, the counter 2 operates (steps), so the data in the ROM can be read out in synchronization with this operation, and the desired timing signal can be easily generated. can do. Since other timing signals can be generated by changing the contents stored in the ROM, the timing signals can be easily changed.

(Effects of the Invention) As is clear from the above embodiments, the present invention is such that a desired timing signal is written in advance in a ROM, and the timing signal is generated by sequentially reading out the desired timing signal, and a simple circuit is used. It has the advantage that a timing signal can be generated depending on the configuration. Furthermore, since other timing signals can be generated by rewriting data in the ROM, the timing signal can be easily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a timing signal generator according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of data written to a ROM and a timing signal corresponding to the write data according to an embodiment of the present invention. . 1...Clock generator, 2...Counter, 3
... ROM. Patent applicant Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] A timing signal generating device includes a read-only memory (ROM), a counter for specifying a read address of the ROM, and a clock generator for operating the counter.