JPH0272711A - Digital filter device - Google Patents

Abstract

PURPOSE:To reduce power consumption by unifying a filter and a decimeter (thinning device) by providing a storage element to hold data with a cycle fg' that is 1/m of a sampling cycle fg separately from a delay element between the delay element and a coefficient multiplier. CONSTITUTION:When a switch Y signal flows on the delay elements (601-608) with the sampling frequency fg, the output of each delay element at a time t1 is set at a state of t1d, and hereafter, it is varied as t2d, t3d... at every sampling cycle. On the other hand, an output signal is outputted sequentially as t10 for the t2d, and t20 for the t2d, and after that, t10, t30... out of the output signals are used. As a result, it is possible to drive the coefficient multiplier or an adder with high power consumption in the filter with an operating frequency fs' at the time of thinning an FIR filter to the sampling frequency fs' that is 1/2 of the sampling frequency fs.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a digital filter device.

(Prior Art) FIG. 1 shows a configuration example of a known FIR type digital filter, in which 101 to 104 are delay elements, 105 to 109 are coefficient units, and 110 is an adder.

Since this filter generally has a flat group delay characteristic, it is preferably used in TV signal processing where waveform transmission is the main purpose.

FIG. 2 is a diagram showing an example of a camera using this FIR filter. R, G, and B signals photoelectrically converted and formed by an image sensor 201 are sent to a sample hold circuit 20.
After being held at 2, it is switched dot-sequentially by a switch 203 to produce a high-band luminance signal, which is converted into a high-band luminance signal by an A/D converter.
/Di conversion, as well as briny correction and gamma conversion, the switch 205 decomposes it again into R, G%B, and each is sent to the FIR filter 207.208.20.
9 and here the band is limited and the RGB matrix 210
to go into. Here, the R1G and B signals are RY=O17R-0, IIB-0, 59G.

The signal is converted into a color difference signal through the conversion B-Y=-0,33G+0.89B-0,59G.

The color difference signal is then modulated by the encoder 211, where bursts are also added to convert it to NTSC (or FAT-, etc.).
A standard television signal is formed.

On the other hand, the luminance signal is the output signal of the A/D converter 204.The luminance signal is band-limited as it is in the FIR filter 213, then a blanking signal is added in the blanking circuit 214, a synchronization signal is added in the adder 215, and the signal is output. The configuration is as follows.

(Problem to be solved by the invention) However, in the above conventional example, there are three Fs in the color signal.
Since one FIR filter is used for the IR filter and the luminance signal, a total of four FIR filters are required, which has the drawback of significantly increasing the circuit size and power consumption during operation.

Therefore, the applicant has proposed a system in which the number of FIR filters can be reduced to two by using FIR filters having a configuration as shown in FIG.

This will be explained below using FIG. 3.

In FIG. 3, 301 is an image sensor, and the R, G, and B signals of each color photoelectrically converted here are held in sample-and-hold circuits 302 to 304, and then are converted into high-bandwidth signals by a switch 305. Form a Y signal. Thereafter, A/D conversion is performed in an A/D converter, and knee correction, gamma correction, and white balance correction are also performed.

Here, the digitized signal is band-limited as a luminance signal by an FIR filter 331, then a blanking signal is added by a blanking circuit 332, and then an adder 73
At step 3, a synchronizing signal is added and output.

On the other hand, color signal processing also uses the same point-sequential Y signal.

The one consisting of 307 to 327 in Fig. 3 is F related to the above-mentioned earlier application.
IR filter, 307 to 314 are delay elements, 3
15 to 323 are coefficient units, 324 to 326 are adders, 33
0 is the controller. This FIR filter is the fourth
The configuration is as illustrated in the figure. That is, three FIR filters: Fl, F2, and F3 are configured using delay elements 307 to 314, coefficient multipliers 315 to 323, and adders 324 to 326 connected in series. For example, at time t1, the outputs of each delay element are Fl, F as shown by the square X in FIG.
2. The outputs of the small F-choice H of F3 are R, G, and B, respectively. At time t2, these are B, R, and G, and at time t3, they are G, B, and R.
And it changes.

327 is a switch for returning the R, G, and B signals that have been separated in this way to the original R, G, and B signals. After this, the R, G, and B signals are converted into color difference signals by an RGB matrix circuit 328. The signal is converted into a standard television signal by an encoder circuit 321, and output.

However, this prior application also had the problem of high power consumption. Generally, as the speed of an IC process increases, its scale tends to increase, and power consumption also increases in accordance with the operating frequency.

Therefore, when configuring a filter, power consumption can be reduced if it can be operated at low speed.

Moving the filter at a low speed all the time is a process of slowing down the sampling speed, which is called thinning. This principle will be explained with reference to FIGS. 5(A), (B), and (C).

- When the sampled digital signal fl is digitized, it is band-limited to its Nyquist frequency fS/2 by a Buri filter. Now, if the sampling period is set to fS = fS/2, if thinning is performed as is, noise called aliasing will occur at the Nyquist frequency of 1°/2. Normally, a digital filter is used to limit the band to fS'/2 and then decimation is performed, but in this case, the filter itself operates at fl, so the power consumption of the filter remains the same as before.

The present invention aims to solve these problems of the prior art.

(Means and operations for solving the interpolation point) In order to achieve such an objective, the present invention provides a temporary storage device in front of the small FIR filter, and further controls the selection switches of Fl, F2, and F3. As a result, the filter and decimator (thinning device) are integrated, thereby reducing power consumption.

(Example) Examples of the digital filter device of the present invention will be described in detail below with reference to the drawings.

FIG. 6 shows a first embodiment of the present invention.

Now, considering the case where the sampling frequency is set to f8/2 with respect to the sampling frequency f1, when the switch Y signal flows to the delay elements 601 to 608 at the sampling frequency fS, the output of each delay element at t is as follows. The state is as shown in t+d in FIG. 6, and thereafter changes to tad, tsd, . . . for each sampling period. On the other hand, the output signals are too for t and d, and t for tgd. Then, among these output signals, j+o, tx. , . . . are used, that is, the output two in the state of tsd, and the output t for each of t4d, tgd, .
4o+t,. , . . . are not used, and the time for this period is
The small FI of F,−F, can be used in the calculation time of 8.
The feature is that latches 613 to 615 are provided in the R filter.

As a result, the FIR filter of the present invention operates the coefficient multiplier and adder, which consume the largest amount of power in the filter, when thinning out to the sampling frequency fS, which is 1/2 the frequency of the sampling frequency fS. It can be driven at a frequency fS'.

FIG. 8 shows a second embodiment of the present invention,
Rather than having a latch on the small FIR side, one latch circuit 608 is provided at the front stage for the common delay element group 601 to 607, and the outputs appearing in the delay elements are set in advance to 613 to 615 in the embodiment shown in FIG. By the latch circuit of t
The configuration is such that a signal held at the timings of +d and tid t @d appears in each delay element.

According to this embodiment, for example, in contrast to the first embodiment,
When thinning a 9TAP filter to 1/2, use a small F
The number of latch circuits included in the IR can be reduced from 9 in the first embodiment to 0, and with regard to delay elements, the sampling frequency f can be reduced in the case of the second embodiment shown in FIG.
Only the latch circuit 608 is driven by S, and the delay element groups 601 to 607 can be driven at half the sampling frequency f1°, so power consumption can be significantly reduced.

Although the first and second embodiments have both described a horizontal FIR filter in signal processing of an RGB image sensor, the present invention is not limited to this. FIR in the direction (
It can also be used for image sensor signals other than RGB (e.g. Mg, C7゜Ye).
, W, etc.) can also be used. Also, the thinning is 1/2
Needless to say, the distance is not limited to 17 m, and can be freely set to 17 m. It goes without saying that this digital filter is not simply limited to camera signal processing.

(Effects of the Invention) As described above, according to the present invention, a filter and a decimator can be integrated, and especially in the filter, the multiplier and adder that consume the most power can be driven at low speed. . This not only makes it possible to significantly reduce power consumption, but also reduces the heat capacity of the IC package, which is effective in downsizing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional FIR filter, Fig. 2 is a block diagram showing an example of a camera using conventional digital signal processing, and Fig. 3 is the configuration of a camera in the earlier application of the present invention. FIG. 4 is a block diagram of the digital filter used in the camera in FIG. 3, FIG. 5 is a diagram for explaining the digital filter and decimation, and FIG. FIG. 7 is a block diagram for explaining the operation of the first embodiment of the present invention. FIG. 8 is a block diagram for explaining the second embodiment of the present invention. . Part 6 Teitomeri Yusho (Method) % Formula % Name of Invention Digital Filter Device 3, Relationship with the Amendment Person Case

Claims (1)

[Claims] (1) In a digital filter that has a plurality of delay elements, a plurality of coefficient units, and one or more adders that create the sum of the outputs of the coefficient units, the period is 1/m with respect to the sampling period f_S, apart from the delay element. A digital filter device having a storage element that holds data at f_S' between the delay element and the coefficient unit.