JPH0272435A - Central arithmetic processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a central processing unit that executes an interrupt program in response to an interrupt input from an external instruction.

[Conventional technology]

Conventionally, a programmable controller using a central processing unit generally controls electrical equipment based on a sequence program input in advance.

The central processing unit of such a programmable controller sends control signals for controlling the electrical equipment to the electrical equipment based on a sequence program in response to various signals sent from the electrical equipment.

In addition, in such a programmable controller, if the interrupt processing execution request signal sent from the electrical equipment has a high priority, the central processing unit will execute the normal program currently being executed or the interrupt program with a low priority. interrupt program and execute the higher priority interrupt program as interrupt processing.

(Problem to be Solved by the Invention) However, there are a plurality of programs executed by the central processing unit as interrupt processing, and each has a predetermined priority order.However, the priority order is determined from electrical equipment. When high-priority program execution requests (interrupt inputs) occur frequently, execution requests for low-priority interrupt programs are not accepted by the central processing unit while this interrupt program is being executed, and control is interrupted. There was a problem that the target electrical equipment would malfunction.

Therefore, the purpose of the present invention is to solve such problems,
An object of the present invention is to provide a central processing unit capable of reliably accepting execution requests of interrupt requests with a low priority even if execution requests of interrupt programs with a high priority occur frequently.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a first storage means that stores a plurality of interrupt programs in advance, and a first storage means that stores a plurality of interrupt programs in advance. a second storage means for sequentially storing program identification numbers; and an arithmetic processing means for reading interrupt programs corresponding to the identification numbers of the second storage means from the first storage means and executing interrupt processing in the order in which the identification numbers are stored. It is characterized by the following.

(Function) In the first embodiment of the present invention, each time a plurality of execution request signals are input, the identification number of the interrupt program that the execution request signal instructs to execute is stored in the second storage means. Even if the processing means is currently executing an interrupt program with a high priority, the arithmetic processing means executes the interrupt programs corresponding to the order of the identification numbers stored in the storage means, that is, the order of input of the execution request signals. As a result, even if requests for execution of interrupt programs with high priority occur frequently, interrupt programs with low priority are also reliably executed.

In addition to the first form, a second form of the present invention is such that when a plurality of execution request signals are simultaneously input, corresponding identification numbers are stored in the second storage means according to a predetermined priority order. Therefore, it is possible to rank the simultaneously input execution request signals.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the basic configuration of an embodiment of the present invention.

In FIG. 1, 100 is a first storage means that stores a plurality of interrupt programs in advance.

Reference numeral 200 denotes a second storage means that sequentially stores the identification number of the interrupt program designated by the execution request signal every time an interrupt processing execution request signal is input from the outside.

Reference numeral 300 denotes an arithmetic processing means that reads interrupt programs corresponding to the identification numbers of the second storage means from the first storage means and executes interrupt processing in the order of the identification numbers.

Further, the second storage means has a storage control means for sequentially storing predetermined (identification numbers of interrupt programs with higher priority) when a plurality of execution request signals are simultaneously input within a certain period of time.

FIG. 2 shows a specific configuration of an embodiment of the present invention.

In FIG. 2, a block IO surrounded by a dashed line indicates the entire central processing unit. This central processing unit IO is also generally called a microcomputer. Reference numeral 1 denotes a central processing unit (CPU), which executes an arithmetic program (control procedure) stored in a read-only memory (ROM) 2.

In addition to the control procedures related to the present invention shown in FIGS. 4 and 5, the ROM 2 roughly stores control procedures for controlling ordinary external equipment.

13 is a random access memory (RA) that temporarily stores various information used when the CPUI executes an arithmetic program.
M). Execution flag 3 related to the present invention is stored in RAM3.
-1 and an order table 3-2 are provided.

Execution flag 3-1 sets the interrupt program to CPIII
The order table 3-2 stores the identification numbers of the interrupt programs requested to be executed in the order in which they were input.

4 is an interface (Ilo) that inputs an execution request signal requesting the CPU to execute an interrupt program from an external device, and transfers input/output signals with normal external devices.
It is.

In this example, by referring to this order table 3-2, the interrupt programs are executed in the order in which the program execution requests are input, and when multiple program execution requests are input at the same time, the interrupt program with the highest priority is executed. is executed first, and then the remaining requests are executed.

FIG. 3 shows a memory map of the order table 3-2 shown in FIG.

In FIG. 3, the order table 3-2 has an area for storing all program numbers of interrupt programs that can be executed as interrupt processing, and execution requests are stored in these areas in the order in which execution requests are input and in consideration of priorities. memorize the program number to be executed. Also, the executed program number in the sequence table 3-2 is erased, and the next program number is stored in the storage area of the executed program number, either the third program number to be executed or the second program number to be executed. The memory area corresponding to the program number to be updated is sequentially updated (bottom-up) by the CPUI.

FIGS. 4 and 5 show a control procedure executed by the CPU shown in FIG. 2, and this control procedure is executed every time an interrupt program execution request signal is inputted to the cp from the outside.

Moreover, FIG. 5 shows the execution order of the interrupt program.

In this example, - as an example, program numbers 60 to 67
It is assumed that interrupt programs are prepared, and the priorities are given in descending order of program number.

When an execution request signal of program number 6o is input to the CPU which is executing a normal program at timing TI shown in FIG. 6, the CPU starts the control procedure shown in FIG. 4 as an interrupt process.

That is, the CPU confirms that there are no execution requests for interrupt programs of 2 fffi or more, and then identifies the program number of the input execution request (step 510-
530).

Next, the CPU writes the number of the program to be executed in the order table 3-2. In this example, the number 6o is written in the storage area of the program number to be executed first in the order table 3-2 shown in FIG. will be written (step 540).

Next, before performing this interrupt processing, that is, writing the interrupt program number to the order table 3-2, the CPU confirms that it is executing a normal program by turning off the execution flag 3-1. , the control procedure shown in FIG. 5 is executed to process the program to be executed first (program number 60 in this example) shown in the order table 3-2 (steps 550→560).
).

In starting the control procedure shown in FIG.
turns on the execution flag 3-1 and stores that the old CP is currently executing interrupt processing. Next, C
P old reads out the number 60 of the program to be executed first from the order table 3-2, reads out the control procedure indicated by this program number from the ROM 2, and executes it (step S61-562).

When the old CP finishes executing this control procedure, it deletes the program number 60 from the order table 3-2.

Subsequently, when it is confirmed that there is no interrupt program to be executed second, the old CP turns off the execution flag 3-1 and returns to the normal control procedure.

Next, the CPU 2 when execution requests for program numbers 65 and 67 are input from the outside to the CP old.
The operation will be explained.

As shown in FIG. 6, when execution requests for program numbers 65 and 67 are input to the CPIII at timing T5 and timing T6 almost simultaneously, the CP
In the old version, the control procedure shown in FIG. 4 is executed.

First, as is done in the conventional example, the old CP determines the priority of the two interrupt programs by determining the I10 port to which the execution request signal is input, and then selects the program with the higher priority. The number 65 is written in the storage area of the program number to be executed first in the order table 3-2. Next, CP old writes the program number to be executed second↑ and writes program number 67 in the Q area (step S10 → S20 → 530 → 540)
.

Next, the old CP moves to the second interrupt control procedure shown in FIG. 5 (steps 550-360), first executing the interrupt control procedure corresponding to program number 65, and then executing the interrupt control procedure corresponding to program number 67. do(
Step 561 → S62 → S63 → S64 → S62~5
64).

If, for example, a program execution request with program number 50 is externally input to the CP old while this interrupt program is being executed, the CP old interrupts the execution of this interrupt program and follows the control procedure shown in Figure 4. Program number 50 is stored in the order table 3-2 in the program number storage area to be executed third. After that, currently the 5th
The execution of the interrupt program shown in the figure is confirmed by turning on the execution flag (step 550), and execution of the interrupt program is resumed.

As explained above, in this embodiment, when multiple execution requests for interrupt programs occur almost simultaneously, the program numbers to be executed are stored in order of priority in order teardown, and then the order table is referred to. Interrupt programs are executed sequentially, and even if an interrupt program with a higher priority occurs in the meantime, it is simply registered in the order table and execution continues, so that execution requests for interrupt programs with a higher priority are frequently issued. Even if a request for execution of a low-priority interrupt program occurs, the central processing unit can reliably accept the execution request.

In this embodiment, when a program number to be executed is registered in the order table 3-2, the program number is deleted from the order table each time the program with that number is executed. If a plurality of program numbers are registered in the order table, the stored contents of the order table may be deleted when the processing of all of the plurality of programs is completed.

〔Effect of the invention〕

As explained above, according to the present invention, the first aspect of the present invention
In this embodiment, each time a plurality of execution request signals are input, the identification number of the interrupt program that the execution request signal instructs to execute is stored in the second storage means, so that the arithmetic processing means can store the identification number of the interrupt program that currently has a high priority. Even when an interrupt program is being executed, the arithmetic processing means executes the interrupt program corresponding to the order of the identification numbers stored in the storage means, that is, the order in which the execution request signals are input. As a result, even if requests for execution of interrupt programs with high priority occur frequently, interrupt programs with low priority are also reliably executed.

In addition to the first embodiment, a second embodiment of the present invention provides that when a plurality of execution request signals are simultaneously input, corresponding identification numbers are stored in the second storage means according to a predetermined order (the highest priority). Therefore, it is possible to rank the simultaneously input execution request signals.

Timing charts 1 to 1 show the processing timing of .

l...CPu 2...ROM 3...l’+AlA 4. Bow 10

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the embodiment of the present invention, FIG. 2 is a block diagram showing the specific configuration of the embodiment of the present invention, and FIG. 3 is the memory of the order table 3-2 shown in FIG. 4 and 5 are flowcharts showing the control procedure executed by the CPU shown in FIG. 2. FIG. 6 shows the control procedure executed by the CPU shown in FIG. 2. Sequence of Cheer 3-2 Melima Noah Fig. 3 Chapter 70 of Propagation of the Present Invention 1 Fig. 5 Flowchart of Practical Example Fig. 4

Claims (1)

[Scope of Claims] 1) A first storage means that stores a plurality of interrupt programs in advance; and each time an external interrupt processing execution request signal is input, an identification number of the interrupt program specified by the execution request signal is inputted. and arithmetic processing means that reads interrupt programs corresponding to identification numbers in the second storage means from the first storage means and executes interrupt processing in the order in which the identification numbers are stored. A central processing unit characterized by: 2) The central processing unit according to claim 1, wherein when a plurality of the execution request signals are simultaneously input within a certain period, the second storage means stores the interrupt program with a predetermined higher priority. A central processing unit characterized in that the central processing unit stores information sequentially starting from the identification number.