JPH0269261A - Phase control circuit in image forming device - Google Patents

Abstract

PURPOSE:To make one phase control circuit deal with all pixels from a low density pixel to a high density pixel by a method wherein a frequency divided output signal is shifted with a constant reference frequency signal, and any one of the shifted output signals is selected with a synchronizing signal in a main scanning direction. CONSTITUTION:For a laser printer, when a power source turns ON irrespective of a reset signal RESETB, a reference oscillator 2 performs oscillating operation, and outputs reference frequency. When the RESET signal becomes at a high level, a frequency dividing circuit starts frequency dividing in a frequency dividing ratio specified with SEL1 to SEL4. A frequency divided clock C9 is inputted to a D terminal of a shift register circuit 25 FF1 shifting at the reference frequency, and the shifted clocks C1 to C8 are respectively inputted to D terminals of FF1 to FF8. Laser beam is incident upon a synchronous detecting sensor. When a DETP signal becomes at a H level, it is latched at its riser edge, and states of the clocks C1 to C8 at that time are outputted to Q terminals of FF1 to FF8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase control circuit in an image forming apparatus such as a laser printer or a digital copier.

(Prior Art) Regarding a laser printer as an example of an image forming apparatus, the relevant parts of the present invention will be briefly explained with reference to FIG. 7, which is a sectional view showing the configuration, and FIG. 8, which shows an optical writing unit for the image.

Each control section of the printer main body (
The recording paper fed from the paper feed unit (upper paper feed 1 to lay 3, lower paper feed tray 4, bulk paper feed tray 5) is The timing is determined by the registration roller pair 6 and the image is conveyed to the photosensitive drum 7 . The photosensitive drum is moved clockwise 19 times, its surface is charged by the charging charger 8, and the laser (LD) from the optical writing unit 9 is charged.
) An electrostatic latent image is formed on the photoreceptor drum by irradiation with light.

Then, as it passes through the developing device 10, it is made into a visible image by toner, and after being transferred onto the recording paper by the transfer charger 11, the visible image is fixed through the fixing device J2 and is discharged.

As shown in the plan view of FIG. 8, the optical writing unit 9 has a laser diode (LD) 13 connected to the engine driver 2.
Controlled by ○N/○FF. This laser beam passes through a collimator lens 14 and a cylindrical lens 15, and enters a polygon mirror 16 rotating counterclockwise, where it is scanned (main scan) as shown by an arrow (A). At this time, the FD lens 17 corrects the scanning speed to be constant at the center and end portions of the writing medium (photosensitive drum 7).

A synchronization detection mirror 19 is disposed at one end of the scan so that the laser beam is detected by a synchronization detection sensor 18 for each scan.

(Problem to be Solved by the Invention) When the engine driver 2 controls the laser diode (LD) 13 of the optical writing unit 9 in 0N10FF to write an image, the phase control circuit that performs image control for a low-speed machine is
Problems arise similar to those used in medium- and high-speed aircraft.

For example, in the case of 20PPM and 480DPI, one image clock is 14MHz, and the image density is half that, 240MHz.
The DPI is about 3.5 old. Therefore, if the same phase control circuit is used and the oscillation frequency of the pixel clock is divided by 8 for medium to high speed machines, the oscillator frequency will be 4.
At 80DPI, it is 112M7 (=14M7x8), and at half that pixel density, 240DPI, it is 28M7 (2), and at high pixel density (480DPI), the 1-phase control circuit (IC gate array) cannot operate. Additionally, devices that operate at high frequencies are expensive.

Furthermore, if the frequency division ratio of the pixel clock is made small, the pixels will become coarser and the image quality will deteriorate in the case of low pixel density.

Therefore, it is conceivable to prepare a phase control circuit corresponding to each pixel density, but this increases the number of parts and increases the cost.

It is an object of the present invention to solve the above-mentioned conventional drawbacks, to enable a single phase control circuit to handle from low-density pixels to high-density pixels, and to reduce costs and improve reliability.

(Structure and operation) In order to achieve the above objects, the present invention includes means for outputting a constant reference frequency, a frequency dividing means whose frequency division ratio for dividing the signal of the constant reference frequency is variable, and a frequency division output thereof. The present invention is characterized in that it is comprised of means for shifting a signal using a signal of the constant reference frequency, and means for selecting any one of the shifted output signals by a synchronization signal 48 in the main scanning direction.

The present invention adds a constant reference frequency output from a reference oscillator to a frequency divider circuit to obtain a plurality of frequency divided outputs. This frequency-divided output is added to a shift register circuit using the reference oscillator output as a clock, and the frequency-divided shift output is selected by a selection circuit, so that a single phase control circuit can generate an image writing clock corresponding to the pixel density. The aim is to reduce cost and improve reliability.

(Embodiment) FIG. 1 shows an image control circuit of a laser printer. In the figure, 20 is a phase control circuit according to the present invention;
LD) light is detected by a synchronization detection sensor 18, and its synchronization signal DETP in the main scanning direction and a clock reset signal CKRETB from the counter 22 are input. It also outputs one image write clock signal WCLKB to the image control circuit 21 and a controller (not shown). This controller is for example a host machine (word processor, computer, etc.)
The character code, etc. sent from
○N10FF is applied to the image control circuit 2.
Indicated by 1.

A counter 22 generates and outputs a line synchronization signal LSYNCB and a line gate signal LGATEB to the controller and the image control circuit 21 according to the image write clock signal WCLKB from the phase synchronization control circuit 20, and also outputs the line synchronization signal LSYNCB and line gate signal LGATEB to the image control circuit 21. Outputs signal 5YNCOB.

Next, the operation will be explained using FIG. 2 showing the timing of each of the above-mentioned signals (DETP, etc.).

In a laser printer, the laser diode (LD) 13 is controlled to emit a constant amount of light before printing, and then when the rotating position of the polygon mirror 16 (Fig. 8) is in front of the synchronization detection sensor 18. Turn on the laser diode (LD) 13. That is, the phase synchronization signal 5Y
NCOB(2) is set to H level. And the laser diode (LD) 13 is connected to the video signal VIDEOB (5).
is set to 0N10FF.

In addition, in the above, the counter 22 is
Counting starts when the laser beam enters the UI detection sensor 18, and is cleared by the next laser beam incident, and counting starts again.

When the laser beam is incident on the polygon mirror 16 rotating counterclockwise and the reflected laser beam is incident on the synchronization detection sensor 18, a synchronization signal DET in the main scanning direction is detected.
P(1) becomes H level, and the rise of this synchronization signal is such that the edge becomes the reference signal of the phase synchronization signal 5YNCOB(2).

3 and 4 show the image writing clock signal WCLKB (7) (second
The frequency division, shift, and selection circuits in Figure 1) are shown.

In the figure, 23 is a reference oscillator that generates a reference frequency;
24 is a frequency dividing circuit, which converts the output frequency of the reference oscillator 23 into CK.
Four flip-flops F input to the terminal and divide the frequency sequentially
F, ~FF4, and four AND circuits AND, ~AND,
and one OR circuit, one input of each AND circuit receives the Q output of FF, ~FFU, and one input receives inputs 5EL1 to S E L4 that select the divided output. . 25 is a shift register circuit having eight flip-flops FF, ~FF, the reference frequency output (clock CLK) from the reference oscillator 23 is input to the CK terminal, and the clocks 01 to C8 are output from the Q terminal. Ru.

In addition, the selection circuit shown in FIG.
flip-flops FF1 to FF, and: (7) FF
1 to FF, (7) Q, NAND circuit NAND, ~NAND, which inputs Q terminal state 8 (H level), AND circuit AND of these NANDs, and frequency division by 6, frequency division by 4, and 2 SEL, which selects the frequency division.

SEL,, 5EL2 is input, and the above NAND, ~N
It is composed of AND, and AND3 that control the operation of AND.

Note that the DETP signal and C
The CKRETB signal is input to the L terminal at the timing shown in FIG.

Next, the operation will be explained using the operation waveforms shown in FIG. 5 (FIG. 6).

In the laser printer, when the power is turned on regardless of the reset signal RESETB, the reference oscillator 23 performs oscillation operation, outputs the reference frequency (clock CLK), and outputs the reference frequency (clock CLK).
When the ET signal becomes H level, the frequency divider circuit 24 selects the selection input 5.
Frequency division is started using the frequency division ratio specified by EL1 to SEL.

That is, the Q output (H
Any one selected (H level) at SEL, SEL, -SEL operates one of AND1-AN, D4. Then, divide the frequency by 8 at SEL=H level, 5
Divide the frequency by 6 when EL2=H level.

SEL, = divided by 4 at H level, 2 at 5EL1 = H level
The frequency division is obtained at the Q terminal of the FF.

The divided clock C, is the reference frequency (clock CLK
) is input to the D terminal of FF□ of the shift register circuit 25, and the shifted clocks C0 to C8 are input to the D terminal of FF, ~FF, respectively, in FIG.
input to the terminal. When the laser beam enters the synchronization detection sensor 18 and the DETP signal becomes H level, this clock C~C1 is latched at the rising edge, and the FF1
The state of the clocks C1 to C at that time is output to the Q and Q terminals of FF. That is, to explain using the example of FIG.
The Q of Fs (C5Q) and the Q of FFG (C6Q) become H level, and only the NAND condition is satisfied, and the clock Ct (bottom row in FIG. 5) as the image write clock WCLKB is output from the AND circuit.

This makes it possible to obtain an image writing clock synchronized with the rotation of the polygon mirror.

When this WCLKB signal is output, the counter 22 shown in FIG. 1 counts and generates the signals 'LSYNCB, LGATEB, etc. shown in FIG. 2 necessary for image formation. Furthermore, at the rising edge of LGATEB (at the rear end of the image in the main scanning direction), the CKRETB signal is output and input to the CL terminals of FF1 to FF to reset the image clock selection circuit (FIG. 4).

In FIG. 6, the frequency is divided by 4 when 5EL3=H level, but at this time, NAND, .about.NAND, does not operate due to the negative operation of AND. In the example of FIG. 6, it is FF.

The Q (CIQ) of FF2 and the Q (C2Q) of FF2 are at the high level, and only the NAND condition is satisfied, so that the clock C (bottom row in FIG. 6) is output as the image write clock WCLKB. The following operation is the same as that shown in FIG. 5, so the explanation will be omitted.

(Effects of the Invention) Since the present invention is configured as explained above, 1.
Since an image writing clock corresponding to the pixel density is obtained by the two phase control circuits, costs can be reduced and image quality is not impaired. Therefore, reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an image control circuit of a laser printer in which the present invention is implemented, FIG. 2 is a diagram showing the timing relationship of the image signals in FIG. 1, and FIG. 3 is a standard according to an embodiment of the present invention. Frequency divider circuit and shift register circuit, 4th
The figure also shows a frequency division output selection circuit, Figures 5 and 6 are waveform diagrams showing image writing clocks divided by 8 and 4, respectively, Figure 7 is a sectional view showing the configuration of a laser printer, and Figure 8 The figure is a plan view of the optical writing unit of FIG. 7. 20... Phase control circuit, 21... Image control circuit, 2
2... Counter, 23... Reference oscillator, 24...
Frequency divider circuit, 25...shift register circuit, FF1~
FF, ... flip-flop, AND, ~AN
D4...AND circuit, NAND, ~N A
ND,...NAND circuit, OR...OR circuit,
5EL1~SEL4...Selection input.

Claims (1)

[Claims] means for outputting a constant reference frequency; a dividing means capable of varying a division ratio for dividing the signal of the constant reference frequency; and means for shifting the divided output signal by the signal of the constant reference frequency; 1. A phase control circuit in an image forming apparatus, comprising means for selecting one of the shifted output signals using a synchronization signal in a main scanning direction.