JPH0266652A - Cache memory - Google Patents

Abstract

PURPOSE:To attain the process continuation of a cache memory by updating the contents of an address array and a data array after detection of a memory error and setting a 2nd additional bit to inhibit the replacement of the address array of the corresponding cache. CONSTITUTION:If an external memory has its abnormality when it receives an access in a memory reading state, the access address is written into an address array 2 together with 'F' set. When the memory receives the second writing action in the same address, a writing action is carried out to a data array 3 of a cache memory since 'F' is set up in the array 2. At the same time, a memory error signal 16 is inhibited by a GT 7 with a memory access given for writing the external memory and therefore never reported to an MPU 100. In the same way, a cache hit state is always kept when the memory is read via the same address since 'F' is set in the array 2. Hereafter the process continues with an access given to a cache memory 1 only.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory, and particularly to a cache memory that serves as an alternative memory when an external storage has a failure.

[Conventional technology]

Conventionally, in information processing systems that use this type of cache memory, when there is a failure in external storage such as main memory, system operation is interrupted even though other cache memories are included. After the fault is removed, the system will resume operation.

[Problem to be solved by the invention]

In the conventional information processing systems mentioned above, even if they have cache memory, system operation is interrupted without using the cache memory as a replacement memory for failed external storage, so normal operation can be resumed. The disadvantage is that it takes a long time to complete.

[Means to solve the problem]

The cache memory of the present invention includes an address array, a valid bit corresponding to each address of the address array, and a data array corresponding to the address array. means for providing a second additional bit in the external memory access, and updating the contents of the address array and data array corresponding to the access address when a memory error is detected during external memory access, and setting the second additional bit; means for prohibiting replacement of the address array of the corresponding cache if the second additional bit is set even in the case of a miss; means to cache if either of the additional bits is set, and the contents of the corresponding data array in the cache if the access address matches the address in the cache and the second additional bit is set at the time of memory writing. It is characterized by comprising means for updating the memory error and prohibiting reporting of memory errors in external storage access to the CPU.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a cache memory of the present invention.

In FIG. 1, a direct mapping type cache memory 1 connected to a microprocessor (hereinafter referred to as MPU) 100 corresponding to a CPU via an address line 10 has a valid bit (hereinafter referred to as "V") and an additional bit (hereinafter referred to as " F
''), and a data array 3 corresponding to the address array 2.
MP)4. Data bus gate circuit (hereinafter referred to as DG) 5, OR circuit (hereinafter referred to as 0R) 6. A gate circuit (hereinafter referred to as GT) 7 is included. Note that 10 is the address line A23 to A2.11.
is a data line, 12 is a read data line from address array 2, 13 is a "V" read line, 14 is an "F" read line,
15 is a cash hit signal, 16 is a memory error signal from external storage, and 17 is a CPU memory error interrupt signal. GT7 inhibits gating of memory error signal 16 when the input signal of "F" read line 14 is 1".

Next, the operation of this embodiment will be explained.

When the memory is accessed, the CMP 4 first checks whether the data exists in the data array 3. To do this, first use the index fields A15 to A2 of the access address as a cache index, select one of the 16 entries in the address array 2 in the cache, and combine this with the access address A23.
~ Check A16 with CMP4. Here, if the comparison results match and "■" or "F" is set, it will be a "catch hit", and the catch hit signal 1 will be output.
5 is sent. If the comparison results do not match, or if ry, , and rF are both 0, it is a "cache miss" and the data is fetched from external storage and this new data is automatically written to the cache. V" is set.

If there is an error in the external memory when accessing the external memory during memory writing, the access address is written to address array 2 and data array 3 in the cache is written.
Write data to , and then set "F". At this time, the memory error signal 16 is sent to the MPU 100 via the GT7.
The MPU 100 recognizes only the report and can continue processing.

If there is an error in the external memory when accessing the external memory during memory read, the access address is set to address array 2.
and set "F". Since the read data at this time is not guaranteed, the MP
It is reported to U100, and MPU100 takes some action.

When memory is written to the same address again, since "F" is set in address array 2, writing is performed to data array 3 of cache memory, and at the same time, memory error signal 1 is generated in memory access to write to external storage.
6 is prohibited by GT7 and is not reported to MPU 100. Similarly, if there is a memory read at the same address, since "F" is set in the address array 2, it will always be a "cash hit", and from then on, only the cache memory 1 will be accessed and processing will continue.

In this embodiment, a direct mapping type cache memory has been described, but the effect is the same even if it is a set associative type cache memory or a fully associative type cache memory.

〔Effect of the invention〕

As explained above, in the cache memory of the present invention, a second additional bit is provided in addition to the valid bit in the address array, and when a memory error is detected during external memory access, the address array and data array corresponding to the access address are At the same time as updating, a second additional bit is set, and even in the case of a cache miss in memory access, if the second additional bit is set, replacement of the address array of the corresponding cache is prohibited, and when the memory is read, the address array is stored in the cache. If the addresses stored in the cache match and either the valid bit or the second additional bit is set, it is considered a cash hit. Also, when writing to the memory, the addresses stored in the cache match and the second additional bit is set. By writing data to the data array in the cache and disabling reporting of memory errors in external memory access to the CPU, the cache memory can be used as a substitute memory for external memory in the event of a failure in external memory. You can use this to continue processing, and even if there is a failure in the cache memory itself, you can continue processing by setting the corresponding additional bit. By reading, it is possible to easily know which external memory is impaired.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a cache memory of the present invention. 1... Cache memory, 2... Address array,
3...Data array, 4...Comparator (CMP), 5
...Data bus gate circuit (DG), 6...OR circuit (OR), 7...gate circuit (GT), 10...
・Address lines A23 to A2.11...Data lines, 15
...Cash hit signal, 16...Memory error signal, 17...CPU memory error interrupt signal, 100
...Microprocessor (MPU), F...Additional bit, ■...Valid bit. Figure 1\, -2

Claims (1)

[Claims] In a cache memory composed of an address array, a valid bit corresponding to each address of this address array, and a data array corresponding to this address array,
A second additional bit is provided in addition to the valid bit corresponding to the address of the address array, and when a memory error is detected during external storage access, the contents of the address array and data array corresponding to the access address are updated, and the second additional bit is added. means for setting a bit; means for prohibiting replacement of the address array of the corresponding cache if the second additional bit is set even in the case of a cache miss in memory access; and means for setting the access address and address in the cache when reading the memory. means for determining a cache hit if they match and either the valid bit or the second additional bit is set; A cache memory comprising means for updating the contents of a corresponding data array in the cache if set, and for prohibiting reporting of a memory error to a CPU in external storage access.