JPH0265295A - Printed board - Google Patents
Printed boardInfo
- Publication number
- JPH0265295A JPH0265295A JP21661788A JP21661788A JPH0265295A JP H0265295 A JPH0265295 A JP H0265295A JP 21661788 A JP21661788 A JP 21661788A JP 21661788 A JP21661788 A JP 21661788A JP H0265295 A JPH0265295 A JP H0265295A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lands
- resist
- land
- adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 abstract description 27
- 239000006071 cream Substances 0.000 abstract description 14
- 238000005476 soldering Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子回路実装基板に使用できるチップ部品用
のランドと隣接する前記チップ部品のランドとの半田接
続を防止するためにチップランドの周囲に印刷するレジ
ストを用いたプリント基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for forming a chip land around a chip land in order to prevent a solder connection between a land for a chip component that can be used in an electronic circuit mounting board and a land of an adjacent chip component. This invention relates to a printed circuit board using a printing resist.
従来の技術
近年、プリント基板は高密度実装化され、実装部品も超
小型化され、集積回路の足リード間隔が小さくなり、実
装時の半田付は品質の向上が望まれている。以下、図面
を参照しながら、上述した2 ・・
従来のプリント基板の一例について説明する。BACKGROUND OF THE INVENTION In recent years, printed circuit boards have been packaged with high density, mounted components have been miniaturized, and the distance between the leads of integrated circuits has become smaller, and it is desired that the quality of soldering during mounting be improved. Hereinafter, an example of the conventional printed circuit board mentioned above will be described with reference to the drawings.
第3図は従来のプリント基板のチップ部品実装ランド及
び隣接する前記チップ部品のランドの半田接続を防止す
るだめのレジストを示すものである。第3図において基
板1」二にはチップ部品ランド3とチップランド接続用
パターンが形成され、そして前記チップランド3と隣接
するランド間及び接続パターン上など、半田不要箇所に
はレジスト2が設けられている。FIG. 3 shows a conventional resist for preventing solder connection between a chip component mounting land of a printed circuit board and an adjacent land of the chip component. In FIG. 3, a chip component land 3 and a chip land connection pattern are formed on a substrate 1''2, and a resist 2 is provided at locations where soldering is not required, such as between the chip land 3 and adjacent lands and on the connection pattern. ing.
以上のように構成された従来のプリント基板では、第4
図に示すように電子部品の半田付は時にチップ部品ラン
ド3上にクリーム半田4を塗布し、前記半田4上にチッ
プ部品6を載置した後、前記半田4を溶融固化させる事
によって、チップ部品6の電極6とランド3とを電気的
に接続する方法(特開昭50−129968号公報)が
あった。In the conventional printed circuit board configured as described above, the fourth
As shown in the figure, soldering of electronic components is sometimes done by applying cream solder 4 on the chip component land 3, placing the chip component 6 on the solder 4, and then melting and solidifying the solder 4. There is a method of electrically connecting the electrode 6 of the component 6 and the land 3 (Japanese Patent Laid-Open No. 129968/1983).
発明が解決しようとする課題
しかしながら、上記のような構成では、チップ部品6の
近接したランド3の間lにレジタ)2A3 /・ 7
があるため、第4図に示すようにチップランド3上に塗
布されたクリーム半田4が、近接ランド方向(X方向)
に流れ出し、半田溶融時に、前記チップランド3が相互
に半田接続される。また、前記クリーム半田塗布後、前
記チップ部品6が載置された時、近接ランド方向(X方
向)にクリーム半田4が流れ出し同様の半田接続を生じ
るという課題を有していた。Problems to be Solved by the Invention However, in the above configuration, since the register 2A3/.7 is located between the adjacent lands 3 of the chip component 6, there is a The applied cream solder 4 is directed towards the adjacent land (X direction)
When the solder melts, the chip lands 3 are soldered to each other. Furthermore, when the chip component 6 is placed after applying the cream solder, the cream solder 4 flows out in the direction of the adjacent land (X direction), resulting in a similar solder connection.
本発明は上記課題に鑑み、近接チップランドに塗布され
たクリーム半田の流出を妨ぐ事により、近接ランド間の
半田接続という不良が発生しないようにしたプリント基
板を提供するものである。In view of the above problems, the present invention provides a printed circuit board that prevents the occurrence of defective solder connections between adjacent lands by preventing the leakage of cream solder applied to adjacent chip lands.
課題を解決するための手段
上記課題を解決するために本発明のプリント基板は、近
接するチップランド間に、その両方に重畳したレジスト
部を設けたものである。Means for Solving the Problems In order to solve the above problems, the printed circuit board of the present invention is provided with a resist portion superimposed on both adjacent chip lands.
作用
本発明は上記した構成によって、チップランド上のクリ
ーム半田はランドのレジスト部の厚みにより横流れが防
止されることとなり、隣接するランド間の半田接続とい
う不良をなくすことが可能である。According to the above-described structure, the cream solder on the chip land is prevented from flowing sideways due to the thickness of the resist portion of the land, and it is possible to eliminate defects such as solder connections between adjacent lands.
実施例
以下、本発明の一実施例のプリント基板について図面を
参照しながら説明する。第1図は本発明の一実施例の平
面図で、第2図はチップ部品を接続した時の断面図であ
る。本実施例では隣接するチップ部品ランド3A 、3
Bの両方に重畳したレジスト部2Bを設けている。EXAMPLE Hereinafter, a printed circuit board according to an example of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view when chip components are connected. In this embodiment, adjacent chip component lands 3A, 3
A resist portion 2B is provided which overlaps both of the resist portions B and B.
以上の様に構成されたプリント基板について、以下第1
図、第2図を用いて、その動作を説明する。チップラン
ド3A 、3B上に塗布されたクリーム半田4は、ラン
ド3人、3B上に重畳されたレジ7)2Bの厚みにより
、横流れを妨ぐ事が出来る。ここで、レジメ)2Bの重
畳する厚みは、クリーム半田の流れ込みを防止するもの
であって、クリーム半田の塗布した厚みと同等、もしく
はそれ以下でも良い。Regarding the printed circuit board configured as above, the following is the first part.
The operation will be explained using FIG. The cream solder 4 applied on the chip lands 3A and 3B can be prevented from flowing horizontally due to the thickness of the register 7) 2B superimposed on the lands 3 and 3B. Here, the overlapping thickness of Regime) 2B is to prevent the cream solder from flowing in, and may be equal to or less than the thickness of the cream solder applied.
以上の様に本実施例によれば、近接するチップランド3
A 、3Bに重畳したレジストを設ける事により、半田
接続を無くし、半田品質の改善を行なう事ができる。な
お、前記実施例でチップ部品として半導体ICを適用し
、電極としてリードを適用すると有効である。As described above, according to this embodiment, the adjacent chip lands 3
By providing superimposed resists on A and 3B, solder connections can be eliminated and solder quality can be improved. In the above embodiments, it is effective to use a semiconductor IC as the chip component and a lead as the electrode.
発明の効果
以上のように本発明は、隣接したチップランドの双方に
重畳するレジストを設ける事により、チップランド上に
塗布されたクリーム半田の横流れを防止することができ
、クリーム半田溶融時のチップランド間の半田接続とい
うショート不良を無くし半田品質の向上を計る事ができ
る。Effects of the Invention As described above, in the present invention, by providing a resist that overlaps both adjacent chip lands, it is possible to prevent the cream solder applied on the chip lands from flowing sideways, and to prevent the chips from flowing when the cream solder melts. It is possible to eliminate short-circuit defects caused by solder connections between lands and improve solder quality.
第1図は本発明の一実施例におけるプリント基板の平面
図、第2図はチップ部品を接続した時の断面図、第3図
は従来のプリント基板の平面図、第4図はチップ部品を
接続した時の断面図である。
1・・・・・基板、2・・・・・・レジスト、3・・・
・・・チップ部品用ランド、4・・・・・・半田、5・
・・・・・チップ部品電極。Fig. 1 is a plan view of a printed circuit board according to an embodiment of the present invention, Fig. 2 is a sectional view when chip components are connected, Fig. 3 is a plan view of a conventional printed circuit board, and Fig. 4 is a plan view of a conventional printed circuit board. It is a sectional view when connected. 1...Substrate, 2...Resist, 3...
...Land for chip parts, 4...Solder, 5.
...Chip component electrode.
Claims (1)
ンド間の双方に重畳するように配設したレジスト部とを
備えた事を特徴とするプリント基板。A printed circuit board comprising adjacent lands for chip components and a resist portion disposed so as to overlap both the adjacent chip lands.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21661788A JPH0265295A (en) | 1988-08-31 | 1988-08-31 | Printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21661788A JPH0265295A (en) | 1988-08-31 | 1988-08-31 | Printed board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0265295A true JPH0265295A (en) | 1990-03-05 |
Family
ID=16691238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21661788A Pending JPH0265295A (en) | 1988-08-31 | 1988-08-31 | Printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0265295A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0661629A (en) * | 1992-08-12 | 1994-03-04 | Unisia Jecs Corp | Printed wiring board |
US5594698A (en) * | 1993-03-17 | 1997-01-14 | Zycad Corporation | Random access memory (RAM) based configurable arrays |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052092A (en) * | 1983-09-01 | 1985-03-23 | 松下電器産業株式会社 | Method of connecting electronic part |
JPS6255375B2 (en) * | 1980-04-01 | 1987-11-19 | Nishimu Denshi Kogyo Kk |
-
1988
- 1988-08-31 JP JP21661788A patent/JPH0265295A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6255375B2 (en) * | 1980-04-01 | 1987-11-19 | Nishimu Denshi Kogyo Kk | |
JPS6052092A (en) * | 1983-09-01 | 1985-03-23 | 松下電器産業株式会社 | Method of connecting electronic part |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0661629A (en) * | 1992-08-12 | 1994-03-04 | Unisia Jecs Corp | Printed wiring board |
US5594698A (en) * | 1993-03-17 | 1997-01-14 | Zycad Corporation | Random access memory (RAM) based configurable arrays |
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