JPH0265138A - Manufacturing method of thin film transistor - Google Patents

Abstract

PURPOSE:To enable self alignment even if the treatment temperature is low by forming a gate insulating film at the surface of the channel region of an active layer, and forming a conductive layer with the gate insulating film as a mask on the source region and the drain region of the active layer. CONSTITUTION:An active layer 105 is formed on a glass substrate 101, and a gate insulating film is formed at the surface of a channel region near the center of the active layer 105, and then a canopy 107 consisting of an n<+>-poly-Si layer is formed at the surface. Next, Al metal is deposited by vacuum from above the surface of the substrate so as to accumulate an Al metallic layer 108. At this time, Al metallic layers accumulated in a source region and a drain region is formed by being masked with the gate insulating film 106 and the canopy 107 at that surface, so it is self alignment. Next, a source metallic layer 109, a drain metallic layer 110, and a gate metallic layer 111 are formed. This way, a thin film transistor that the self alignment is possible even if the treatment temperature is low can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application IIj] The present invention relates to a method for manufacturing a thin film transistor, and particularly to a method for manufacturing an N-film transistor that allows self-alignment even at low processing temperatures during the process.

[Conventional technology] Thin film transistors were used as switching elements.

In response to the needs of an information society, active matrix liquid crystal displays and image sensors that use film transistors as shift register elements, etc., are becoming larger in screen size and reading size. These thin film transistors are currently formed on the surface of relatively large silicon or quartz substrates, but if a glass substrate with a larger area and lower cost could be used, it would be possible to fully meet the needs. By the way, the conventional method for manufacturing thin film transistors is, for example, using single-layer & silicon (0-Si)
Or polycrystalline silicon', t (poly-S i)
In order to make the source and drain regions self-aligned with the gate insulating film, predetermined impurities are doped into the source and drain regions by ion implantation or thermal diffusion using the gate insulating film as a mask. It includes the process of introducing In addition, amorphous silicon (α-
5L) The manufacturing method of the %J film transistor made of the material is as follows:
First gate 1! It included a step in which self-alignment was impossible, such as forming the active layer after forming the electrode and gate insulating films.

[Problems to be Solved by the Invention] These conventional techniques have important drawbacks as listed below. In other words, (1) Impurity introduction techniques such as ion implantation or thermal diffusion raise the substrate temperature to 1000°C to activate the impurities.
An annealing process is required at a high temperature around ℃, but even if a heat-resistant substrate is used at this time, the substrate expands and contracts due to the temperature cycle, resulting in misalignment of the pattern and deterioration of patterning accuracy. .

(2) Transparent heat-resistant substrates that can withstand high-temperature annealing include quartz substrates, but the size of these substrates is limited and they are very expensive.

Active substrates for LCDs with a screen size of 10 inches or more include 7059 glass substrate (manufactured by Corning) and 0A-2 glass substrate (manufactured by NEC Corporation), but their heat resistance is limited to around 600°C. Therefore, it cannot be used in a process involving high-temperature annealing as described above.

(3) Although the glass substrate described above can be used in a low temperature process of 400° C. or less like α-31, self-alignment cannot be achieved, so element characteristics vary and parasitic capacitance increases.

There were 811 questions such as

Therefore, the present invention is intended to solve the above-mentioned problems, and its purpose is to fabricate poly-Si with good device characteristics on a large glass substrate with a low heat-resistant temperature.
Another object of the present invention is to provide a method for manufacturing a thin film transistor that can be formed by self-aligning a thin film transistor made of a 0-3i material.

[Means for Solving the Problems] A method for manufacturing an H-film transistor of the present invention is a method for manufacturing a thin film transistor having an insulated gate structure formed on an insulating substrate, in which an active layer of the transistor is formed on the surface of the insulating substrate. forming a gate insulating film on a surface of a channel region of the active layer; and forming a conductive layer in at least a source region and a drain region of the active layer using the gate insulating film as a mask. It is characterized by

[Example code] The present invention will be further explained in detail based on Examples.

(Example 1) As a first example of the present invention, a method for manufacturing a thin film transistor using a vapor deposition method for self-alignment will be described. FIG. 1 explains a first embodiment of the present invention, and is a cross-sectional view of a substrate showing a manufacturing process of a thin film transistor using a vapor deposition method. Figure 1 (α) is a cross-sectional view of the substrate after thinning deposition.
Poly-31 layer 102.1 SooK silicon dioxide (Sin) layer 105.1oooL phosphorus (P) doped n+-poly-S 1 layer 104 is successively la layered. A low pressure OVD method is used to deposit these thin films.
The glass substrate was heated to 600°C, and monosilane gas (SiH
4) Deposition was performed continuously using oxygen (OX), phosphine (PHs), and helium as a carrier gas. FIG. 1(A) is a cross-sectional view of the substrate after the gate insulating film is formed. The non-doped poly-S 1 layer 102 is etched into an island shape to form an active layer 105, and the gate insulating film is formed on the surface of the channel region near the center of the active layer 105. A film 106 is formed, and an eaves 107 made of one layer of n-poly-S is formed on the surface thereof. Here, the width and length of the gate insulating film 106 are smaller than those of the eaves 107, and the four side walls of the gate insulating film are deeper inside than those of the eaves. This structure can be manufactured by etching SL and 02 for a longer time after forming the eaves 107. 1st, Figure (
c) is a cross-sectional view of the substrate after forming a conductive layer. A4 metal layer 108 is deposited by vacuum evaporating At metal upward on the substrate surface. At this time, the At beam that comes flying during evaporation is almost perpendicular to the substrate surface, and is not deposited on the active layer under the protrusion of the eaves 107 or on the side surfaces of the gate insulating film 106, and becomes the gate electrode and the bottom of the eaves 107. A on the surface
The t metal layer is electrically completely isolated from the A/metal layer of the source or drain region. The At metal layer deposited on the source and drain regions is self-aligned because it is masked by the gate insulating film 106 and the eaves 107 on its surface. Note that the thickness of the At metal layer 108 is
It is thinner than the gate insulating film and is approximately 10ooX. 1st
Figure (d) shows the source metal layer 109. drain metal layer 110
．． FIG. 5 is a cross-sectional view of the substrate after forming gate metal J5111.

After sintering the At metal layer, the At metal layer was patterned by photoetching.

Figure 1 (i is a cross-sectional view of the substrate of the completed thin film transistor. After coating the substrate surface with photosensitive polyimide, contact holes were opened and cured at 400°C to achieve passivation fN112.!:. After that, A7
= Depositing metal and patterning source electrode 113. Drain electrode 114 and gate? I! A pole 115 was formed.

The thin film transistor manufactured in this manner exhibited enhancement type Le channel characteristics, an electron field effect mobility of 18 d/V-El, and an 0N10F'IP ratio of 6 digits or more.

Note that in this example, po'Ly -Si is used in the active layer.
Although the material used is limited to this, 0-3i may also be used.
A silicon nitride film, alumina, etc. can also be used as the gate insulating film material. The eaves may be made of any conductive material and may be made of other semiconductor materials or metals.

(Example 2) As a second example of the present invention, a method for manufacturing a thin film transistor using a selective deposition method as a means of self-alignment will be described. FIG. 2 explains a second embodiment of the present invention, and is a cross-sectional view of a substrate showing a method of manufacturing an N-film transistor by a selective deposition method.

FIG. 2(α) is a cross-sectional view of the substrate after thin film deposition, and the structure and deposition method are the same as those in FIG. 1(α) described in Example-1. FIG. 2(b) is a cross-sectional view of the substrate after forming a gate insulating film, in which the active layer 205 is formed by etching the doped poly-S1 layer 202 into an island shape, and then the gate is etched near the center of the active layer 205. Insulating film 2
06 and a gate electrode 207 are formed. Figure 2 (C)
An n+ type poly-Si film 208 is selectively deposited only on the poly-8i surfaces of the source region, drain region, and gate electrode. The selective deposition method of the poly-Si film is as follows. First, the substrate shown in FIG. 2(b) was placed under reduced pressure (set in the IVD device, 3 T+)rr
Purge the substrate surface sufficiently with an inert gas under a reduced pressure of
Introduce process gas. The process gas is first introduced with hydrogen chloride (HOl) gas diluted with an inert gas, and then, in addition thereto, dichlorosilane (5iH2c12) gas and PH gas diluted with an inert gas are introduced. When dichlorosilane gas is introduced, poly-S
At this time, so-called selective deposition occurs, in which the i film is deposited only on the underlying po:Ly-Si surface and not on the glass substrate or the SiO□ film.At this time, PH is thermally decomposed and the po
1y! P is doped into the El film to form a highly concentrated n-type poly-Si film. The thickness of the selectively deposited n+ type poly-Si film must be thinner than that of the gate insulating film, and care must be taken not to short-circuit the source region or drain region with the gate electrode. d) is a cross-sectional view of the completed thin film transistor. After selective deposition, a SiO film 209 is formed as an interlayer insulating film on the surface of the substrate by sputtering, a contact hole is opened, and a source is formed using vapor-deposited At metal. Electrode 210: At metal forming the drain electrode 211 and gate electrode 212 and n-type po 1y-8
The i-film was sintered at 500°C to establish ohmic connection.

In this example, an n+ type po
ly Si film was selectively deposited, but the method is not limited to this, for example, p+ type poly into which diborane (BzHa) gas is introduced.
It is also possible to manufacture a thin film transistor in which a -Si film is selectively deposited.

FIG. 3 is a cross-sectional view of a substrate in which an n-channel thin film transistor and a p-channel thin film transistor are formed on the same substrate in an application of this embodiment. It is intended for the construction of an 0M0S logic circuit on a glass substrate. An n-channel thin film transistor 302 and a p-channel thin film transistor 503 are formed on a 0A-2 glass substrate 301. Active parts 304 of both thin film transistors. Gate insulating film 305
, gate electrode 3069 interlayer insulating film 309 and electrode 51
0 is formed in the same process and is an n-type pO1y-Si film 30
7 and the p-type poly-Si film 308 were formed in separate steps. That is, the steps in the same process are the same as the respective steps shown in FIG. When forming the -Si film, each n-channel thin film transistor region was protected with a passivation film.

The method for manufacturing the thin film transistor described in the above embodiments is as follows:
This method can be used as a method for manufacturing switching transistors for pixels in active matrix liquid crystal displays, plasma displays, image sensors, etc., and transistors constituting 0MO3 circuits for drivers.

[Effects of the Invention] The present invention has the special effects of the invention listed above.

(1) Since self-alignment is possible at low temperatures below 600°C, thin film transistors with excellent characteristics can be manufactured using inexpensive, large-area glass substrates.

(2) Self-alignment has become possible, and the tolerance range for alignment accuracy due to expansion and contraction of the substrate has been expanded, improving manufacturing yield.

(3) Since self-alignment is possible, thin film transistors with small input capacitance can be formed, and therefore, when a logic circuit or the like is constructed, the operating speed can be greatly improved.

[Brief explanation of the drawing]

FIGS. 1(α) to CI=) illustrate a first embodiment of the present invention, and are cross-sectional views of a substrate showing a manufacturing process of a thin film transistor using a vapor deposition method. FIGS. 2(α) to 2(d) illustrate a second embodiment of the present invention, and are cross-sectional views of a substrate showing a method of manufacturing a thin film transistor by a selective deposition method. FIG. 5 is a cross-sectional view of a substrate in which an n-channel thin film transistor and a p-channel thin film transistor are formed on the same substrate in an application of this embodiment. 101.201...Glass substrate 105.205
......Active layer 106.206...Gate insulating film 107
...Eaves 108 ...At metal layer 109
. . . metal layer 110 . . .
...Drain metal layer 111 ...Gate metal layer 208.507...N-type poly
-Si film 50B...p-type poly
-Si film diagram

Claims (1)

[Claims] (1) A method for manufacturing a thin film transistor having an insulated gate structure formed on an insulating substrate, including the steps of forming an active layer of the transistor on the surface of the insulating substrate, and forming a gate insulating film on the surface of the channel region of the active layer. (2) Forming the conductive layer (2) Forming the conductive layer using the gate insulating film as a mask 2. The method of manufacturing a thin film transistor according to claim 1, wherein the step includes a selective deposition step.