JPH0264728A - Page description language processor - Google Patents

Abstract

PURPOSE:To execute a page description language at high speed by providing a main CPU to control the execution of plural sub-CPUs, the sub-CPUs to generate page memory data, plural FIFO memories, a transfer CPU, etc. CONSTITUTION:In a page description language execution part 102 composed of a main CPU 103, sub-CPUs 106-107, FIFO memories 10-109, a CPU 110, etc., the CPU 103 controls the execution of the sub-CPUs and the sub-CPUs generates the page memory data. The memories 108-109 have a first-in first-out function and send the data of the sub-CPUs to the CPU 110. Thus, CPU 110 transfers and writes input data to a page memory 114 in the same sequence as the sequence of the text string of the page description language and executes a page description language text at high speed. By providing a function that the main CPU executes the processing while the sub-CPUs generate the data, a dummy code generating means, a transfer confirmation means, etc., to the memory 114, etc.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a multi-CPU system that executes page description language text.
The present invention relates to a page description language processing device of the configuration.

[Prior art]

With the spread of LBPs (laser beam printers), page description languages such as Po5t5script, which allow a host computer to control the printer's page memory, have become popular. Typical page description language pos
The specifications of tscript are (Adobe System
Inc.: Po5t 5crypt Language
age: Reference Manual, Ad
dison-Wesley, 1985), (Ado
beSystem Inc.: Po5t 5cr
ipt Language:Tutorial
and Cookbook, Addison-Wes
ley.

1985), (Page Description Language PDLI, published by East Co., Ltd.).

Conventionally, a single microprocessor on a printer interface sequentially interprets and executes a text string in a page description language sent from a host computer. However, as high-speed printers become more widespread, there is a demand for faster execution of text strings in page description languages.

Po5t 5crip, a typical page description language
t is a format in which text strings stored in a stack are sequentially interprinted and executed. A function expressed as a text string (for example, the function paint-draws a line segment in the X direction (1w
arc - Drawing the circumference of an arc (etc) is highly independent, and the functions that require a large amount of calculation are mainly functions that generate page memory data (for example, the function gr cur
Since the ve-curve is drawn ( ), it is thought that speeding up can be achieved by executing functions for generating each page memory data in parallel by multiple CPUs. However, if the results of parallel calculations by multiple CPUs are simply written to the page memory, the original execution order of the functions is no longer guaranteed, and the generated page memory data may become incorrect.

〔the purpose〕

In view of the above points, the present invention has a main CPU that manages the execution of multiple CPUs, multiple CPUs that generate page memory data, and a memory having a FIFO function that retains data sent out from each of the multiple CPUs. and FIFO
An object of the present invention is to provide a page description language processing device capable of realizing high-speed execution of a page description language by means of writing data from a functional memory to a page memory in the same order as a text string from a host computer. It is said that

〔Example〕

The present invention will be described in detail below with reference to Examples.

1 to 14 show a first embodiment of the present invention.
The drawings best represent the features of the present invention.

In the figure, 101 is a host computer (input unit) that generates and sends out a page description language text string. 10
2 is a page description language execution unit that interprets and executes a text string from the host computer.

The main CPU 103 is a microprocessor that controls the sub-CPU I-N, 106 to 107, executes all functions except those for generating data in the page memory 114 and clip memory 111, performs loop control, and performs four arithmetic operations. do.

104 to 105 are common memories, and the main CPU 10
3 and the sub CPUs 106 to 107.

Sub CPUs 106 to 107 are a plurality of microprocessors controlled by main CPU 103 and execute functions for generating data in page memory 114 or clip memory 111.

FIFO-1108 to FIFO-N 109 are Fir
It is a buffer memory with a st-IN-First-OUT function, and stores the data of the sub CPUs 106 to 107.
The receiver plays the role of passing the data to the CPU-z 110.

CPU-zllo is a microprocessor and FIF
Data transferred from O-1108 to FIFO-N 109 is transferred to clip memory 111 or page memory 11.
Transfer to 4.

The clip memory 111 is a memory for performing clipping, and is composed of a page memory and a bitmap memory corresponding to pixels. If the bit of a pixel in the clip memory 111 is 1, data is not written to the page memory at the corresponding address. do not have. The initial value of the clipping memory 111 is 0.

The image management memory 112 stores font memory and graphic data memory for outputting character data, and is generated and managed by the main CPU 103.

Page memory 114 is a memory in which print data is stored. In this embodiment, the page memory 114 is 1
It is composed of a multilevel memory with L pixel bits.

The common memory zl13 is used by the main CPU 103 and the CPU-
This is a common memory for zllo, and serves as a synchronous memory for the main CPU 103 to know when the operation of CPU-zllo has ended.

The printer main unit 115 is a multivalue printer, and is controlled by the main CPU 103 to print out data in the page memory 114.

FIG. 2 shows common memory 1 104 to common memory N 10.
FIG. 5 is a configuration diagram of No. 5.

The synchronization flag 201 is the main CPU 103 and sub CPU 1
It plays the role of synchronizing execution with 06-107.

Function text area 202 is for sub CPUs 106 to 107
This is an area where the function name and arguments to be executed are stored as strings.

The management data area 203 is the function text area 202.
Main CPU1
Set by 03.

Figure 3 shows the main CPU 103 and sub CPUs 106 to 10.
7 is a state transition diagram regarding synchronous control of No. 7. FIG. Synchronization flag 2
Relationships such as on/off of 01, function execution, etc. are described.

FIG. 4 is a configuration diagram of the common memory zl 13, which is configured by a synchronization flag 401.

Figure 5 shows sub CPUs 106 to 10 of the main CPU 103.
7 is a processing flowchart regarding operation management of No. 7; FIG.

At 5501, the main CPU 103 extracts text from the text stack in which the text string sent from the host computer 101 is stored. The text stack is configured on the memory of the main CPU 103.

In step 5502, the main CPU 103 determines whether the text is one that generates page memory data or clip memory data (for example, in the case of the POSTS CRIPT language, gr c
urve: Draw a Bezier curve (,s 1ni
tclip: initialize clip memory, etc.) It is determined whether this is the case, and if page memory data or clip memory data is to be generated, process 5503 is executed; otherwise, process 5504 is executed.

In step 5504, the main CPU 103 determines whether the text is device control text, that is, print execution text (for example, PO
STSCRIPT language devpag for PC98 version
eout) etc., processing 5505 is executed, otherwise processing 5506 is executed.

Process B of 5503 performs the process shown in FIG.

Process C of 5505 performs the process shown in FIG.

At 8506, the main CPU 103 executes processing other than the functions determined at 5502 and 5504.

FIG. 6 is a process flowchart when the text is page memory or clip memory generated text (process 5503 in FIG. 5).

Current CPU No. 5601 means the number of the sub CPU that the main CPU 103 most recently requested processing.
Increase by 1. Current CPU number is main CPU10
3. This is a variable value held internally.

In 5602, the current CPU-No is the number N of sub CPUs.
Determine whether or not it exceeds the limit, and if it does, proceed to process 56.
Do 03.

5604, common memory 1 104 to common memory N 1
05, check whether the synchronization flag 201 of the common memory n corresponding to the current CPU-N0=n is on or off, and if it is on, repeat the above process until it becomes off, and if it is off, Process 3605 is performed.

At 5605, the function text area 20 shown in FIG. 2 is displayed for the common memory n corresponding to the current CPU-N0=n.
2 and management data area 203 are set.

At 8606, the synchronization flag 201 of the common memory corresponding to \current CPU-N0=n is turned on.

FIG. 7 is a processing flowchart of the main CPU 103 when the text from the host computer 101 is device control text.

5701, main CPU 103 is common memory 1 104
~ Check whether all the synchronization flags in the common memory N105 are off or not. If even one is on, repeat the process of S701.

In 5702, the main CPU 103 checks whether the synchronization flag of CPU-zllo is off, and if it is on, repeats the process of S702.

By carrying out the above processes 5701 and 5702, it is guaranteed that all the page memory generation processes that existed until the execution of the device command text have been completed by the time the next process 8703 is executed.

5703, the main CPU 103 is the printer main unit 115
Executes device commands such as printing and printer initial settings.

FIG. 8 is a processing flowchart of the sub CPUs 106-107.

At 5801, it is checked whether the synchronization flag 201 of the common memory n is on, and if it is on, the next process at 8802 is performed.

Check the function text area 202 in 5802, and if the function generates page memory data, perform the process in 5803, and if the function generates clip memory data, perform the process in 5802.
807 processing is performed.

8803 converts page memory data to function text area 2
02 and the contents of the management data area 203.

In 5804, it is checked whether page memory data has been generated by the process in 8803. For example, if text data has not been generated due to some function text abnormality,
06 is performed, and if page memory data has been generated, processing 5805 is performed.

At 5805, the generated data is transferred to FIFO-n in the data structure shown in FIG.

5806, the dummy code 901 shown in FIG.
-Forward to n.

Through the processing in steps 3804 to 8806, even if page memory data is not generated due to a function error, F
Data can be transferred to IFO-H, and CPU-
It is possible to prevent zllO from falling into an infinite loop while transferring data from FIFO-n.

At 5807, clip memory data is generated based on the contents of the function text area 202 and the management data area 203.

In 8808, it is checked whether or not clip memory data has been generated by the process in 8807. If clip memory data has been generated, the process in 5809 is performed, and if no clip memory data has been generated, the process in 810 is performed.

At 5811, the synchronization flag of common memory n is turned off.

In FIG. 9, sub CPUs 106 to 107 are FIF0108
This is the data formation of the dummy code to be transferred to 109, and all O's are stored. When the gummy code 901 appears, the CPU-zllo takes out the data for the corresponding FIFO memory, ends the process, and accesses the next FIFO memory.

In FIG. 10, sub CPUs 106 to 107 are PIF010
This is data formation of page memory data to be transferred to pages 8 to 109, and 1 (hexadecimal) is stored in the identifier 1001.

1002 indicates the X address of the page memory 114, and 1
003 indicates the Y address of the page memory 114. 10
04 is page memory data. In this embodiment, the page memory 114 is a multi-value memory, and correspondingly, the page memory 1004 stores L-bit multi-value data.

Figure 11 shows the data format of the clip memory flowing in the FIFO memory, and the identifier 1001 is 2 (hexadecimal).
is stored.

FIGS. 12 and 13 are diagrams showing the x and y coordinate printing directions of the page memory and clip memory, respectively.

FIG. 14 is a flowchart regarding the processing of CPU-zllo.

51401"QCPU-zllO is a variable held inside the CPU: FIF indicated by current FIFON0=n
Read data for O-n. When data exists in FIFO-n, processing 1402 is performed, and when data does not exist, processing 51411 is performed.

Synchronization flag 401 of common memory z1513 at 51411
Turn off.

51402 checks whether the data received from FIFO-n matches the dummy code 901 and if it matches, returns 31.
The process of 408 is performed, and if there is no match, the process of 51403 is performed.

Synchronization flag 401 of common memory z1513 in 51403
Turn on.

At 51404, it is checked whether the data received from FIFO-n is page memory based on the value of the identifier shown in FIGS. 10 and 11, and if it is page memory data, 51
The process of 405 is performed, and if it is clip memory data, the process of 51407 is performed.

51405, X of the corresponding page memory data.

Check whether the clip memory data corresponding to the Y address is on or off, and if it is off, perform the process 51406,
If it is on, the process returns to step 51401.

At 51406, page memory data is written corresponding to the x and Y addresses.

At 51407, the receiver writes data to the clip memory corresponding to the received x9Y address.

As is clear from the explanation of FIG. 14 above, the CPU-zll.

requires relatively simple logic to be executed quickly. Therefore, a microprogrammable high speed processor or central processing unit, ROM memory and high speed cache RA
A so-called one-chip processor in which M is integrated is desirable.

On the other hand, the main CPU 103 is required to execute a large number of functions and to manage a large capacity memory such as the image management memory 112 that contains font data, etc., so a so-called 32-bit microprocessor such as 68020 (manufactured by Motorola) is preferable. .

[Other Examples]

15 to 17 relate to the second embodiment of the present invention.

In the first embodiment, as shown in FIG. 6 604, when the sub CPU-n was executing a function, it had to wait until the execution was completed.

In the second embodiment, by providing a FIFO memory connected to the main CPU 103 and transferring data to the CPU-zllO, when a sub CPU requesting function execution is in execution, the main CPU 103 It executes a function. As a result, the main CPU10
3 can be used effectively, and the processing parallelism of the entire device can be increased.

FIG. 15 is a block diagram regarding the second embodiment, and
IFO-x1506 is a CPU from main CPU1513
- It is a FIFO memory that transfers data to the z1510.

FIG. 16 is a processing flowchart of the second embodiment of the main CPU 1503, and corresponds to FIG. 6 604 of the first embodiment. The main CPU 1503 and other processing are the same as in the first embodiment.

FIG. 17 is a processing flowchart regarding the second embodiment of the CPU-z1510.

First, in step 51701, it is determined whether or not there is data in the current FIFO-n, and if there is not, in step 51702, the synchronization flag 401 of the common memory 2 is turned off. Next, in step 31703, it is determined whether the data in the current FIFO-n is a dummy code. If NO, proceed to 51704, and common memory 2
51704), and determines whether the data is page memory data (S1705).
.

If NO, the process advances to 51706, writes to the clip memory, and returns to 51701.

Also, if Yes in 51705, proceed to 51707 to determine whether the corresponding clip memory is on (51707); if No, proceed to 51708 to write the data to the page memory; if Yes, proceed to 51707). 517
Return to 01.

If 51703 is Yes, that is, the current FI
If the data stored in FO-n is a dummy code, the current PIFONO is increased by 1 in S1709.

Next, in 51710, it is determined whether the current PIFONo is greater than N. If NO, proceed to 51712, Y
If it is es, proceed to 51711 and select the current PIFON.

=1. Next, proceed to 81712. In 51712,
It is determined whether there is data in FIFO-x 1516.

If Yes, it is determined in step 51713 whether the data stored in FIFO-x 1516 is a dummy code. Yes
If it is s, the process returns to 51701. If NO, 51714
Go to , turn on the synchronization flag 401 of common memory 2,
51715 determines whether the data is page memory or not, and N
If O, write to clip memory with 31716, 5
Returning to 1712, if Yes, turning on the corresponding clip memory at 51717, writing data to the page memory at 51718, and returning to 51712.

FIG. 18 relates to a third embodiment of the present invention.

In the first embodiment described above, data was written to the page memory only from the page description language execution unit 102, but in this embodiment, data read from the image scanner 1801 is stored in the page memory 1802. , in the page memory 1802 in which image scanner data is stored,
From the page description language execution unit 1803 to the page memory 180
Data is written to 2. With this, for example, it is possible to read a gradation surface of a photograph or the like from the image scanner 1801, write an explanatory text from the page description language execution unit 1803, and print out the combined image.

〔Effect of the invention〕

As explained above, there is a main CPU that manages the execution of multiple CPUs, multiple CPUs that generate page memory data, a buffer memory that holds data sent out from multiple CPUs, and a page description language that stores the data in the buffer memory. By writing the page description language text into the page memory in the same order as the text string, it is possible to execute the page description language text at high speed.

In addition, when the sub CPU controlled by the main CPU executes a function, if memory write data is not generated, it is possible to prevent the processor that writes data to memory from falling into an infinite loop by generating gummy code. .

Furthermore, if a sub-CPU controlled by the main CPU is executing a function when the main CPU attempts to make an operation request, by providing a means for the main CPU to calculate the function, the degree of parallel processing of the device can be increased. You can improve your climbing ability.

Also, when executing device control such as printing or reading image scanner data, the main CPU confirms that all data generated by the sub CPU controlled by the main CPU has been written to the page memory or clip memory.
By providing a means for the PU to confirm, normal execution of device control can be guaranteed.

Furthermore, by having a microprocessor connected to the buffer memory write the data generated by the sub-CPU into the page memory or clip memory via the buffer memory, clipping can be achieved very simply and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment. FIG. 2 is a configuration diagram of common memory 1104 to common memory N105. Figure 3 shows the main CPU 103 and sub CPUs 106 to 1.
The state transition diagram regarding the synchronous control of 07. FIG. 4 is a configuration diagram of the common memory zl13. FIG. 5 shows the sub CPUs 106 to 1 of the main CPU 103.
2 is a processing flowchart regarding operation management of No. 07. FIG. 6 is a process flowchart when the text is page memory or clip memory generated text. FIG. 7 is a processing flowchart of the main CPU 103 when the text from the host computer 101 is device control text. FIG. 8 is a processing flowchart of the sub CPUs 106-107. In FIG. 9, sub CPUs 106 to 107 are FIF0108
~ Data format of Gummy code to be transferred to 109. In Figure 10, sub CPU-106 to 107 are PIF01
Data format of page memory to be transferred from 08 to 109. FIG. 11 shows the data format of the clip memory flowing in the FIFO memory. FIG. 12 shows the x and y coordinates of page memory. Figure 13 shows the x and y coordinates of the clip memory. FIG. 14 is a flowchart regarding the processing of CPU-zllO. FIG. 15 to FIG. 17 are process flowcharts regarding the second embodiment. FIG. 18 is a processing flowchart regarding the third embodiment. 102・・・・・・・・・・・・・・・・・・・・・ Song page description language execution unit 103・・・・・・・・・・・・・・・
・・・・・・・・・・・・Main CPU106~107
・・・・・・・・・・・・Sub CPUIO3~lO9・
Song song sub CPU106~107 (7) data to CPU
FIFO memory 110 to be transferred to Z-110 ・ ・ ・ Microprocessor 111 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
...Clip memory 112...
...Pause... Image management memory 113
・・・・・・・・・・・・・・・・・・・・・・・・
・114 ・・・・・・・・・・・・・・・・・・
・・・・・・・・・1501 ・・・・・・・・・・・・
・・・・・・・・・・・・1502 ・・・・・・・・・
・・・・・・・・・・・・・・・1503 ・・・・・・
・・・・・・・・・・・・・・・1504～1505
・・・・・・ 1506～1507 ・・・・・・ 1510 ・・・・・・・・・・・・・・・・・・
・・・1513 ・・・・・・・・・・・・・・・
......Common memory page memory between CPU-zllo and main CPU 103 Host computer Page description language execution unit Main CPU Common memory sub-CPU Common memory page memory between microprocessor CPU-z1510 and main CPU 503 Image scanner page memory Page Description Language Execution Department 躬 2 图力 9 强 10 图 MAN j 1 图Mo 图

Claims (4)

[Claims] (1) A main CPU that is a device that processes text expressed in a page description language and that interprets the text.
It has multiple sub-CPUs controlled by the main CPU, and a buffer memory that holds page memory data generated by the sub-CPUs, and the buffer memory data is stored in the page memory in the same order as the text string. A page description language processing device having a means for transferring. (2) The page according to claim 1, wherein if the sub CPU is generating data at the time when the main CPU requests the sub CPU to process, the main CPU executes the process. Descriptive language processing device. (3) If page memory data or clip memory data is not generated when the sub CPU generates data,
A page description language processing device according to claim 1, comprising means for generating a dummy code. (4) After the main CPU confirms that all page memory data or clip memory data generated by the sub CPU or main CPU has been transferred to the page memory or clip memory, and after performing the above confirmation operation, the main CPU 2. A page description language processing device according to claim 1, wherein the page description language processing device executes a device control command.