JPH0262799A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the number of works for the relief of a defective memory cell by providing a control means to decide the specific order of priority in relation to the selection of a redundant memory cell array or plural redundant memory cell rows at the time relieving the defective memory cell. CONSTITUTION:A redundant memory cell array A or B is selected for a defective memory cell array, a control circuit 100 to function permutation selects either of two redundant memory cell arrays A and B from outside against one of the defective memory cell arrays in a normal memory cell array 101 through a program circuit including a fuse and the like and the permutation is feasible. In the case of the relief of one defective memory cell array, the redundant memory cell array B close to the memory cell array 101 side which is small in the difference of the high density and the low density of the periodic circuit element and has less fluctuation of a circuit element in its production process, namely the redundant memory cell array B difficult to be defective, is selected out of the two redundant memory cell arrays A and B and permuted. Thus, possibility able to permute one defective memory cell by one time can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for repairing defective memory cells in a semiconductor memory device, and more particularly to specifying the priority order of redundant memory cells to be selected.

[Prior Art] Conventionally, in this type of defective memory cell relief method, a plurality of replaceable redundant memory cell columns (rows) exist for one defective memory cell, and when defective memory cells are rescued, one defective memory cell is One redundant memory cell column (row) per column (row)
At that time, select which redundant memory cell column (row) out of the multiple replaceable redundant memory cell columns (rows) for one defective memory cell column (row) and replace it. There was no consideration as to whether to do so.

[Problems to be Solved by the Invention] In the conventional defective memory cell relief method described above, a replaceable redundant memory cell column (row) is divided into one defective memory cell column (
row), and when repairing a defective memory cell, one
One redundant memory cell column (
At that time, for one defective memory cell column (row), select which redundant memory cell column (row) out of the multiple replaceable redundant memory cell columns (rows) and replace it. For example, if a redundant memory cell column (row) is placed at the edge of a memory cell array, redundant memory cell columns (rows) closer to the memory cell array and closer to the peripheral circuitry were not considered. Side redundant memory cell column (row)
In this case, there are differences in the density of the circuit elements around those redundant memory cell columns (rows), resulting in variations in the circuit elements.
Redundant memory cell columns (rows) closer to peripheral circuits are more likely to become defective. In this way, one defective memory cell column (
For each redundant memory cell column (row) that can be replaced, the probability of becoming defective is not necessarily equal. , when one defective memory cell is selected and replaced, there is a high probability that this selected redundant memory cell column (row) will become defective, and another new redundant memory cell column (row) is selected again. However, there is a disadvantage that there is a high possibility that the replacement will have to be redone, and the number of operations required to repair the defective memory cell increases.

[Differences between the invention and the prior art] In contrast to the above-described conventional defective memory cell relief method, the present invention provides a method for repairing one defective memory cell column (row) from a plurality of redundant memory cell columns (rows) that can be replaced. , when one redundant memory cell column (row) is selected and replaced with a defective memory cell column (row), a plurality of redundant memory cells 1 (row) that can be replaced with one defective memory cell column (row) are selected. A selection order is provided, and one redundant memory cell column (row) is selected for one defective memory cell according to the priority order,
The difference is that a replacement is performed.

[Means for Solving the Problems] A method for repairing defective memory cells in a semiconductor memory device according to the present invention uses a plurality of redundant memory cell columns (rows) that can replace one defective memory cell column (row). When selecting one redundant memory cell column (row) and replacing it with a defective memory cell,
The control means provides a priority order for selection of a plurality of redundant memory cell columns (rows).

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, and the first embodiment is an example including two redundant memory cell columns. Selecting redundant memory cell column A or B for the defective memory cell column,
The control circuit 100 responsible for replacement is configured to read the regular memory cell array 101 from the outside by a program circuit including fuses and the like.
It is possible to select one of the two redundant memory cell columns A and B to replace one defective memory cell column in the memory cell column. When repairing one defective memory cell column,
Of the two redundant memory cell rows, the redundant memory cell row B is closer to the memory cell array 101 side, where the difference in the density of the circuit elements in the period is small and there is little manufacturing variation in the circuit elements, that is, the redundant memory cell row that is less likely to become defective. Select B and perform replacement. To achieve this, a control circuit 10 selects a redundant memory cell column for a defective memory cell column and performs replacement.
By externally programming a program circuit including a 0 fuse, etc., a redundant memory cell column B that is unlikely to become defective is selected and replaced with a defective memory cell column.

FIG. 2 illustrates a second embodiment of the present invention.

The difference from the first embodiment is that a redundant memory cell row A'B' is selected for a defective memory cell row, and a redundant memory cell row is selected for a defective memory by a program circuit including the output of a row decoder 201 and a fuse. The purpose is to select and replace a defective memory cell row using the output of the circuit 202 that controls replacement. In this embodiment, for one defective memory cell row, a redundant memory cell row B' near the memory cell array side is replaced with two redundant memory cell rows A'.
, B' and perform replacement.

[Effects of the Invention] As explained above, the present invention has the following advantages: from a plurality of redundant memory cell columns (rows) that can replace one defective memory cell,
When one redundant memory cell column (row) is selected and replaced with a defective memory cell, the selected priority order is set for multiple redundant memory cell columns (rows) that can be replaced with one defective memory cell. , multiple redundant memory cell columns (rows) that can be replaced for one defective memory cell are arranged in an order in which they are less likely to become defective.
Among the multiple redundant memory cell columns (rows) that can be replaced for one defective memory cell, one redundant memory cell column (row) that is unlikely to become defective is selected and replaced, and the replaced redundant memory cell column (row) becomes defective, and the possibility of replacement with another redundant memory cell column (row) is small. The effect is that there is a high possibility that it only needs to be done once. In addition, especially when there are four redundant memory cell columns (rows) that can be replaced for one defective memory cell, the one with the highest probability of not becoming defective among the four redundant memory cell columns (rows) If the redundant memory cell column (row) is known, replacing the defective memory cell with that redundant memory cell column (row) will reduce the possibility that the replaced redundant memory cell column (row) will become defective. The present invention is very effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a first embodiment of the present invention;
FIG. 2 is a block diagram illustrating a second embodiment of the present invention. 100...Circuit (control means) for controlling selection and replacement of defective memory cells to redundant memory cell columns, 101.phi.memory cell array, 201...Row decoder, 202...Setting defective memory cells to redundant memory cells Control circuit (control means) for controlling selection/replacement to cell rows, A, B...redundant memory cell columns, A', B"...redundant memory cell rows. Patent applicant: NEC Corporation Agent Patent Attorney Kiyoshi Kuwai - Figure 1 Figure 2 Jun

Claims (1)

[Claims] A semiconductor memory device having a plurality of redundant memory cell columns or a plurality of redundant memory cell rows and capable of replacing a defective memory cell in a normal memory cell array with a redundant memory cell,
1. A semiconductor memory device comprising control means for setting a specific priority for selecting a redundant memory cell column or a plurality of redundant memory cell rows when repairing a defective memory cell.