JPH0262676A - Rough wiring device - Google Patents

Abstract

PURPOSE:To realize a wiring with high density by executing the channel wiring algorithm and then the wiring in an LSI after storing the net connecting information, the relative positional relation between cell areas, an upper/lower limit graph into a memory. CONSTITUTION:Each wiring net and the cell area relative position are read into a net connecting information memory 1 and a cell area relative position memory 2 respectively. An upper.lower limit flag is produced from the contents of both memories 1 and 2. The channel wiring algorithm is applied to the upper/ lower limit flag via a channel wiring processor 5 for calculation of a channel area where the horizontal segment of each net is wired. Then the net vertical component is wired between a channel area where the horizontal segment of each net passes and a cell are where the nets are connected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a schematic wiring device for LSI automatic layout,
In particular, the present invention relates to a schematic wiring device for increasing the density of schematic wiring within an LSI.

[Conventional technology]

Conventionally, when performing general wiring of an LSI, a method has been adopted in which elements (wiring nets) to be wired are taken out one by one and their wiring routes are determined one by one.

[Reference Kobe, et al.: “A Placement Algorithm for Polycel Ernis Eye and Its Engineering Valuation”
AIgorit,hm for Polycel
l LSI and its Evaluat
ion), Proceedings of the 1981 Design Automation Conference (Proc.

Design Automation Conference
nce) [Problem to be Solved by the Invention] Schematic wiring in LSI automatic layout is, as shown in Figure 2, a method that, when given LSI cell areas and wiring requirements (wiring nets) between them, The goal is to determine a wiring route that meets the requirements.

In the conventional method, the wiring nets are processed one by one, so depending on the order of the wiring, the wiring that was drawn earlier (for example,
Net 1) in Figure 2 is the wiring (
This poses a problem in that it becomes a hindrance to the net 2) in the figure and increases the chip area of the LSI.

The purpose of the present invention is to develop a channel routing method, which is a bilocal routing method [Reference: ``Efficient Algorithm for Channel Routing'' (Ef.
ficient Algorithms for Ch.
annel Routing), 1981 IE Transaction Computer Aided Design Volume C.N.D.-1
Number 1 (IEEE Trans, Compu
ter-Aided Design, Vol.

The object of the present invention is to provide a schematic wiring device that realizes high-density wiring by processing wiring nets all at once by applying CAD-I No. 1)].

[Means to solve the problem]

The schematic wiring device of the present invention includes a net connection information storage device that stores net connection information, a cell area relative position storage device that stores relative positional relationships between cell areas, and an up and down constraint graph storage device that stores up and down constraint graphs. A channel wiring processing device that executes a channel wiring algorithm; and a constraint device that executes wiring within an LSI using each of the above devices.

[Effect]

Generally, two or more wiring nets connect terminals, but here it is assumed that each wiring net is disassembled to connect two terminals. It is also assumed that each net can freely pass over the cell in the vertical direction.

Such a net set is N= +nl l nz...
), and the row numbers of the cells to which the terminals connected to net n1 belong are li and ui (li≦ui).

At this time, the wiring channel ci through which the horizontal component of each net passes, which satisfies the following conditions, is determined.

Condition 1: When 1i=ui, 11≦ci≦ui+Condition 2:
When Ii<ui, 11+1≦ci≦U [Example] Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a schematic wiring device of the present invention.

In the figure, a net connection information storage device 1 (device 1) stores net connection information, and a cell area relative position storage device 2 (device 2) stores the relative positional relationship between cell areas.

The upper and lower constraint graph storage device 3 stores upper and lower constraint graphs. Channel wiring processing device 4 executes a channel wiring algorithm. The restriction device 5 uses each of the devices described above to
Execute wiring within SI.

The contents of the vertical constraint graph will be explained using FIGS. 3 and 4. Each node of this graph corresponds to a cell area or a horizontal component of a wiring net. Also, from node i to node j
An arc pointing towards indicates that node i is located above node j.

In the example of FIG. 3, net a corresponds to the above condition 2 and is wired between channel region j and i, so on the vertical constraint graph, the node corresponding to cell region i is connected to the node corresponding to net a. , and a technique is applied from the node corresponding to net a to the node corresponding to cell area k.

Similarly, since condition 1 applies to net b, two branches are attached to net b.

Next, the operation of the schematic wiring device of the present invention will be explained.

Step 1: Set the relative position of each wiring net and cell area to device 1.
, and are read into the device 2, respectively.

Step 2: Create a vertical constraint graph from the contents of devices 1 and 2.

Step 3: A channel wiring algorithm is applied to the above-mentioned vertical constraint graph by the channel wiring processing device to calculate the channel area in which the horizontal line segment of each net is to be wired.

Step 4: Wire the vertical component of the net between the channel region through which the horizontal line segment of each net passes and the cell region to which the net connects.

〔Effect of the invention〕

As described above, the use of the channel wiring algorithm has the effect of satisfying the above condition 1.2 and realizing highly dense wiring.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the schematic wiring and wiring device of the present invention, Fig. 2 is an explanatory diagram of a cell region, wiring channel, and wiring net, and Figs. 3 and 4 are an explanation of vertical constraint graphs. It is a diagram. DESCRIPTION OF SYMBOLS 1... Net connection information storage device, 2... Cell area relative position storage device, 3... Vertical constraint graph storage device, 4
... Channel wiring processing device, 5... Control device.

Claims (1)

[Claims] a network connection information storage device that stores network connection information;
A cell area relative position storage device that stores relative position relationships between cell areas, an up/down constraint graph storage device that stores an up/down constraint graph, and a channel wiring processing device that executes a channel wiring algorithm; A schematic wiring device comprising a constraint device that executes wiring within an LSI.