JPH0261803B2 - - Google Patents
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- Publication number
- JPH0261803B2 JPH0261803B2 JP56070993A JP7099381A JPH0261803B2 JP H0261803 B2 JPH0261803 B2 JP H0261803B2 JP 56070993 A JP56070993 A JP 56070993A JP 7099381 A JP7099381 A JP 7099381A JP H0261803 B2 JPH0261803 B2 JP H0261803B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- signal source
- output
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
Description
本発明はサンプラを用いて高調波ミキシングを
行うことにより、高周波信号を低周波信号に変換
する周波数変換回路に関するものである。
高周波信号を試験素子(例えばコンデンサ、抵
抗器、増幅器等)に印加して、該素子の高周波特
性を測定する場合、測定を容易にするため、該試
験素子の出力信号を低周波信号に変換して測定す
ることが一般に行なわれる。
第1図は従来の周波数変換回路のブロツク図で
ある。図において、サンプラ3は入力高周波信号
源1の出力信号4(周波数fOで、例えば増幅器、
コンデンサ、抵抗器等の試験素子を通過した信
号)とサンプルパルス発生器13の出力信号6
(サンプル周波数fS)とを高調波ミキシングし周
波数fM′の出力信号10を発生する。ここでサン
プルパルス発生器13の出力信号6はフエーズロ
ツクループ(PLL)回路2を用いて発生される。
PLL回路2は信号4と6を高調波ミキシングす
るサンプラ5、該サンプラ5の出力信号と基準信
号(周波数fM)8とを受信する位相検出器7、ロ
ーパスフイルタ9を介して位相検出器7の出力信
号を受信する電圧制御型可変周波数信号発生器
(VCO)11,VCO11の出力信号を受信して
パルス信号を発生するサンプルパルス発生器13
により構成される。PLL回路2はサンプラ5の
出力周波数がfMに等しくなるように動作する。こ
こでサンプルパルス発生器13の出力は、周波数
fSの幅の狭いパルス信号であるので高調波成分を
多く含んでいる。したがつてサンプラ3の出力信
号10の周波数fM′はfM′=fM=fO±nfS(nはサン
プル次数または高調波次数で自然数)となる。よ
つて差成分をフイルタで抽出すれば入力高周波fO
を一定低周波fMに変換しうる。しかしながらこの
回路は次の2つの欠点を有する。入力周波数fO
が変化した場合、それに応じた周波数fSを得るに
は、PLL回路2が同期する時間が必要である。
上式のnが一義的に定まらず、同じ入力周波数
fOでも異なる次数nで周波数変換する。次数nが
変わるとサンプリング効率が変わるため、サンプ
ラ3の入力信号に対する出力信号の振幅や位相情
報に誤差を生ずる。また次数nが不明であるとサ
ンプリング効率の変化に対する補償量も決定でき
ない。なお従来サンプル次数を一義的に定める回
路が存在するが非常に複雑である。
本発明は上記欠点を除去するためになされたも
ので、本発明の主たる目的は、入力周波数が変化
した場合でも、必要なサンプル周波数信号を得る
ための同期時間がほぼ零で、且つ同じ入力周波数
に対して常に同じサンプル次数で周波数変換を行
う周波数変換回路を提供することである。
本発明の他の目的はサンプル次数を一義的に且
つ任意の自然数に設定可能な周波数変換回路を提
供することである。以下図面を用いて本発明を詳
細に説明する。
第2図は本発明の一実施例による周波数変換回
路のブロツク図である。図において21は入力高
周波信号源(周波数fO)、23は、所望の一定低
周波数fM(サンプラ25の出力周波数)だけ周波
数fOより低い周波数fO−fM信号を発生する信号発
生器、27は信号発生器23の出力信号を1/N
(Nは自然数)に分周する分周器、29は分周器
27の出力信号を受信して該分周器の出力周波数
fSと等しい周波数の幅の狭いパルス信号を発生す
るサンプルパルス発生器、25は入力高周波信号
源21とサンプルパルス発生器29との出力信号
を高調波ミキシングして出力信号22(周波数
fM′)を発生するサンプラである。
上記構成による周波数変換回路は次のように動
作する。サンプルパルス発生器29および分周器
27の出力周波数fSはfS(fO−fM)/Nとなる。
サンプラ25の出力周波数fM′は
fM′=fO=fO±n・fS=fO±n・fO−fM/N(nはサ
ンプル次数で自然数)となる。ここでサンプラ2
5の出力端にはnの値に依存する複数個の周波数
成分が存在するが、該出力端に周波数fMの信号成
分を抽出するフイルタを接続しておけば、n=N
のときに限つてfM′=fMなる信号が抽出され、希
望する周波数変換が行なわれる。即ち周波数fMの
出力信号成分はn=Nの高調波ミキシングによる
出力信号である。ここでNの値は一義的に且つ任
意の値に設定可能であり、また同一周波数fOに対
しては同じNの値を設定すれば常に同一のn(=
N)次高調波成分による周波数変換が行なわれ
る。さらにかかる周波数変換回路は、入力信号源
21と信号発生器23との信号を2径路でサンプ
ラ25に印加するオープンループ回路であり、
PLL回路を有しないから、入力周波数fOが変化し
た場合、fSも同時に変化する。よつて引き込みや
同期に要する時間がほぼ零で、必要なサンプル周
波数fS信号を瞬間に得ることができる。信号源2
1とサンプラ25との間に試験素子を接続すれ
ば、該素子の高周波特性を低周波に変換して測定
できる。
第3図は第2図に示した信号発生器の詳細ブロ
ツク図を含む本発明の他の実施例による周波数変
換回路のブロツク図である。図において点線で囲
んだ部分20が信号発生器23の詳細ブロツク図
である。20はPLL回路であり、入力高周波信
号源21と電圧制御型可変周波数発振器(VCO)
35との出力信号を受信するミキサ39、ミキサ
39の出力信号を受信するローパスフイルタ3
7、ローパスフイルタ37と基準信号源32(サ
ンプラ25の出力所望周波数fMを発生する)の出
力信号を受信する位相検出器31、位相検出器3
1の出力信号を受信してその出力信号をVCO3
5に印加するフイルタ33により構成される。よ
つてVCO35はfOに対してfMだけ周波数の異なる
信号fO〓fMを発生する。fOをfM′(=fM)に変換す
る動作は第2図の場合と同一である。なお、本実
施例の場合には、信号源21の出力信号を一つの
入力信号とするPLL回路を使用しているので、
位相同期に要する時間を必要とする。しかし、n
=Nの値は一義的に且つ任意の値に設定可能であ
る。
第4図は本発明のさらに他の実施例による周波
数変換回路のブロツク図である。この回路は広範
囲の入力周波数を低周波数に変換しうる回路であ
る。第2図の回路と同一部分には同一符号を付し
て示した。43は信号源41(周波数fV)と信号
源45(周波数fO)の出力信号を混合して周波数
fの信号を発生する第1ミキサ、47は信号源4
1と信号源49(周波数fO〓fM)の出力信号を混
合して周波数f±fMの信号を発生する第2ミキサ
である。よつて第2ミキサ47の出力には、第1
ミキサ43の出力信号の周波数とfM(所望の出力
周波数)だけ異なる周波数の信号が発生される。
ここで信号源45は第2図の信号源21と、信号
源49は第2図の点線部分20と等価である。こ
こでfO、fO〓fMを一定にしておき、fVを可変にす
ればfを広範囲に可変することができる。したが
つて第1ミキサ43とサンプラ25との間に試験
素子を接続すれば、該素子の広範囲にわたる周波
数特性を低周波に変換して測定することができ
る。周波数変換動作は第2図の場合と同一であ
り、n=Nのときに限つてfM′=fMとなり、Nの
値を一義的に且つ任意の値に設定できる。また、
信号源41の出力信号を入力信号とするPLL回
路を使用していないので、オープンループ回路で
あり、fVを変化させても引き込みや位相同期に要
する時間はなく、サンプルパルス発生器29より
瞬時に所望の出力信号が発生する。なおサンプラ
25の動作上、fSの値にはある範囲があるため、
fVを可変した場合、Nの値を連動して変化させ
る。以下に本回路の動作を具体的数値で示す。
The present invention relates to a frequency conversion circuit that converts a high frequency signal into a low frequency signal by performing harmonic mixing using a sampler. When applying a high frequency signal to a test element (e.g. capacitor, resistor, amplifier, etc.) to measure the high frequency characteristics of the element, the output signal of the test element should be converted to a low frequency signal to facilitate the measurement. Generally, measurements are carried out using FIG. 1 is a block diagram of a conventional frequency conversion circuit. In the figure, the sampler 3 is connected to the output signal 4 of the input high-frequency signal source 1 (at frequency f O , e.g. from an amplifier,
signals passed through test elements such as capacitors and resistors) and the output signal 6 of the sample pulse generator 13
(sample frequency f S ) to generate an output signal 10 of frequency f M '. Here, the output signal 6 of the sample pulse generator 13 is generated using a phase lock loop (PLL) circuit 2.
The PLL circuit 2 includes a sampler 5 that performs harmonic mixing of the signals 4 and 6, a phase detector 7 that receives the output signal of the sampler 5 and a reference signal (frequency f M ) 8, and a phase detector 7 that passes through a low-pass filter 9. A voltage-controlled variable frequency signal generator (VCO) 11 receives the output signal of the VCO 11, and a sample pulse generator 13 receives the output signal of the VCO 11 and generates a pulse signal.
Consisted of. The PLL circuit 2 operates so that the output frequency of the sampler 5 becomes equal to fM . Here, the output of the sample pulse generator 13 is the frequency
Since it is a pulse signal with a narrow f S width, it contains many harmonic components. Therefore, the frequency f M ′ of the output signal 10 of the sampler 3 becomes f M ′=f M =f O ±nf S (n is the sample order or harmonic order and is a natural number). Therefore, if the difference component is extracted with a filter, the input high frequency f O
can be converted into a constant low frequency f M . However, this circuit has two drawbacks: Input frequency f O
When the PLL circuit 2 changes, time is required for the PLL circuit 2 to synchronize in order to obtain the corresponding frequency fS .
n in the above equation is not uniquely determined, and the input frequency is the same
Frequency conversion is also performed at f O with a different order n. Since the sampling efficiency changes when the order n changes, errors occur in the amplitude and phase information of the output signal with respect to the input signal of the sampler 3. Furthermore, if the order n is unknown, the amount of compensation for changes in sampling efficiency cannot be determined. Although there is a conventional circuit that uniquely determines the sample order, it is extremely complicated. The present invention has been made to eliminate the above-mentioned drawbacks, and the main object of the present invention is that even if the input frequency changes, the synchronization time to obtain the necessary sample frequency signal is almost zero, and the input frequency remains the same. An object of the present invention is to provide a frequency conversion circuit that always performs frequency conversion with the same sample order. Another object of the present invention is to provide a frequency conversion circuit that can uniquely set the sample order to any natural number. The present invention will be explained in detail below using the drawings. FIG. 2 is a block diagram of a frequency conversion circuit according to one embodiment of the present invention. In the figure, 21 is an input high-frequency signal source (frequency f O ), and 23 is a signal generator that generates a frequency f O −f M signal lower than frequency f O by a desired constant low frequency f M (output frequency of sampler 25). , 27 converts the output signal of the signal generator 23 to 1/N
(N is a natural number), 29 receives the output signal of the frequency divider 27 and outputs the frequency of the frequency divider.
A sample pulse generator 25 generates a narrow pulse signal with a frequency equal to f
It is a sampler that generates f M ′). The frequency conversion circuit with the above configuration operates as follows. The output frequency f S of the sample pulse generator 29 and the frequency divider 27 is f S (f O −f M )/N. The output frequency f M ′ of the sampler 25 is f M ′=f O =f O ±n·f S =f O ±n·f O −f M /N (n is the sampling order and a natural number). Here sampler 2
There are multiple frequency components depending on the value of n at the output end of 5, but if a filter is connected to the output end to extract the signal component of frequency f M , n=N
Only when , the signal f M ′=f M is extracted and the desired frequency conversion is performed. That is, the output signal component of frequency f M is an output signal resulting from harmonic mixing where n=N. Here, the value of N can be uniquely set to any value, and if the same value of N is set for the same frequency f O , the same n (=
Frequency conversion is performed using N)-order harmonic components. Furthermore, this frequency conversion circuit is an open loop circuit that applies signals from the input signal source 21 and the signal generator 23 to the sampler 25 through two paths,
Since it does not have a PLL circuit, if the input frequency fO changes, fS will also change at the same time. Therefore, the time required for acquisition and synchronization is almost zero, and the required sample frequency f S signal can be obtained instantaneously. Signal source 2
By connecting a test element between 1 and the sampler 25, the high frequency characteristics of the element can be converted to low frequencies and measured. FIG. 3 is a block diagram of a frequency conversion circuit according to another embodiment of the invention, including a detailed block diagram of the signal generator shown in FIG. A portion 20 surrounded by a dotted line in the figure is a detailed block diagram of the signal generator 23. 20 is a PLL circuit, which includes an input high frequency signal source 21 and a voltage controlled variable frequency oscillator (VCO)
a mixer 39 that receives the output signal from the mixer 35; and a low-pass filter 3 that receives the output signal of the mixer 39.
7. A phase detector 31 and a phase detector 3 that receive the output signals of the low-pass filter 37 and the reference signal source 32 (which generates the desired output frequency f M of the sampler 25).
Receive the output signal of 1 and send that output signal to VCO3
The filter 33 applies the voltage to the voltage. Therefore, the VCO 35 generates a signal f O 〓 f M which has a frequency different from f O by f M. The operation of converting fO into fM ' (= fM ) is the same as in the case of FIG. In addition, in the case of this embodiment, since a PLL circuit is used which uses the output signal of the signal source 21 as one input signal,
Requires time for phase synchronization. However, n
The value of =N can be uniquely set to any value. FIG. 4 is a block diagram of a frequency conversion circuit according to yet another embodiment of the present invention. This circuit is capable of converting a wide range of input frequencies to lower frequencies. Components that are the same as those in the circuit shown in FIG. 2 are designated by the same reference numerals. 43 is a first mixer that mixes the output signals of signal source 41 (frequency f V ) and signal source 45 (frequency f O ) to generate a signal of frequency f; 47 is signal source 4;
1 and the output signal of the signal source 49 (frequency f O 〓f M ) to generate a signal of frequency f±f M . Therefore, the output of the second mixer 47 includes the first
A signal whose frequency differs from the frequency of the output signal of mixer 43 by f M (desired output frequency) is generated.
Here, the signal source 45 is equivalent to the signal source 21 in FIG. 2, and the signal source 49 is equivalent to the dotted line portion 20 in FIG. Here, by keeping f O and f O 〓f M constant and making f V variable, f can be varied over a wide range. Therefore, by connecting a test element between the first mixer 43 and the sampler 25, the frequency characteristics over a wide range of the element can be converted to low frequencies and measured. The frequency conversion operation is the same as in the case of FIG. 2, and only when n=N, f M '=f M , and the value of N can be uniquely set to any value. Also,
Since it does not use a PLL circuit that uses the output signal of the signal source 41 as an input signal, it is an open-loop circuit, and even if fV is changed, there is no time required for pull-in or phase synchronization, and the sample pulse generator 29 generates an instant signal. The desired output signal is generated. Note that due to the operation of the sampler 25, the value of f S has a certain range, so
When f V is varied, the value of N is changed in conjunction. The operation of this circuit is shown below using specific numerical values.
【表】
以上説明したことより明らかなように、本発明
によれば分周器の分周比によりサンプル次数を一
義的に且つ任意の値に設定することができ、所望
の周波数変換を行うことができる。また入力周波
数が変化しても瞬時にかかる変換を行うことがで
きる。[Table] As is clear from the above explanation, according to the present invention, the sampling order can be uniquely set to any value by the frequency division ratio of the frequency divider, and desired frequency conversion can be performed. Can be done. Further, even if the input frequency changes, such conversion can be performed instantaneously.
第1図は従来の周波数変換回路のブロツク図、
第2図は本発明の一実施例による周波数変換回路
のブロツク図、第3図は第2図に示した信号発生
器の詳細ブロツク図を含む本発明の他の実施例に
よる周波数変換回路のブロツク図、第4図は本発
明のさらに他の実施例による周波数変換回路のブ
ロツク図である。
1,21:入力高周波信号源、3,5:サンプ
ラ、7,31:位相検出器、9,33,37:フ
イルタ、11,35:電圧制御型可変周波数発振
器、13,29:サンプルパルス発生器、23,
32,41:信号源、27:分周器、39,4
3,47:ミキサ。
Figure 1 is a block diagram of a conventional frequency conversion circuit.
FIG. 2 is a block diagram of a frequency conversion circuit according to one embodiment of the present invention, and FIG. 3 is a block diagram of a frequency conversion circuit according to another embodiment of the present invention, including a detailed block diagram of the signal generator shown in FIG. 4 are block diagrams of a frequency conversion circuit according to still another embodiment of the present invention. 1, 21: Input high frequency signal source, 3, 5: Sampler, 7, 31: Phase detector, 9, 33, 37: Filter, 11, 35: Voltage controlled variable frequency oscillator, 13, 29: Sample pulse generator ,23,
32, 41: Signal source, 27: Frequency divider, 39, 4
3,47: Mixer.
Claims (1)
波数fより所望の周波数fM′だけ異なる周波数f
−fMの信号を発生する第2信号源と、前記第2信
号源の出力信号を分周する分周器(分周比=N)
と、前記分周器の出力信号を受信してサンプルパ
ルス信号を発生する回路と、前記第1信号源の出
力信号と前記サンプルパルス信号とを受信して高
調波ミキシングを行なうサンプラと、前記サンプ
ラの出力信号より前記所望の周波数fMの信号成分
を抽出するフイルタとより成り、前記第2信号源
の出力信号は前記サンプラの出力信号を用いるこ
となく発生され、前記フイルタの出力信号に対す
る前記高調波ミキシングのサンプル次数nはn=
Nによつて一義的に決定されるようにしたことを
特徴とする周波数変換回路。 2 前記第2信号源は、前記第1信号源の出力信
号と電圧制御型可変周波数発振器の出力信号とを
受信するミキサと、ローパスフイルタを介した前
記ミキサの出力信号と前記所望の周波数fMを発生
する基準信号源の出力信号とを受信する位相検出
器と、フイルタを介して前記位相検出器の出力信
号を前記電圧制御型可変周波数発振器に与える手
段とより成る位相ロツクループで構成され、前記
電圧制御型可変周波数発振器の出力を出力信号と
する信号源である特許請求の範囲第1項記載の周
波数変換回路。 3 前記第1信号源は、可変周波数信号源と、第
3信号源と、前記可変周波数信号源と前記第3信
号源の出力信号を受信し出力信号を発生する第1
ミキサとで構成され、前記第2信号源は、前記可
変周波数信号源と、前記第3信号源の出力周波数
より所望の周波数fMだけ異なる周波数の信号を発
生する第4信号源と、前記周波数可変信号源と前
記第4信号源の出力信号を受信し前記第1ミキサ
の出力周波数とは前記所望の周波数fMだけ異なる
周波数の出力信号を発生する第2ミキサとで構成
される特許請求の範囲第1項記載の周波数変換回
路。 4 前記第4信号源は、前記第3信号源と電圧制
御型可変周波数発振器の出力信号を受信するミキ
サと、ローパスフイルタを介した前記ミキサの出
力信号と前記所望の周波数fMを発生する基準信号
源の出力信号とを受信する位相検出器と、フイル
タを介して前記位相検出器の出力信号を前記電圧
制御型可変周波数発振器に与える手段とより成る
位相ロツクループで構成され、前記電圧制御型可
変周波数発振器の出力を出力信号とする信号源で
ある特許請求の範囲第3項記載の周波数変換回
路。[Claims] 1. A first input signal source and a frequency f that is different from the output frequency f of the first signal source by a desired frequency f M '.
A second signal source that generates a signal of -f M , and a frequency divider that divides the output signal of the second signal source (dividing ratio = N)
a circuit that receives the output signal of the frequency divider and generates a sample pulse signal; a sampler that receives the output signal of the first signal source and the sample pulse signal and performs harmonic mixing; and the sampler. a filter for extracting the signal component of the desired frequency f M from the output signal of the second signal source, the output signal of the second signal source is generated without using the output signal of the sampler, and the output signal of the second signal source is generated without using the output signal of the sampler; The sample order n of wave mixing is n=
A frequency conversion circuit characterized in that the frequency conversion circuit is uniquely determined by N. 2. The second signal source includes a mixer that receives the output signal of the first signal source and the output signal of the voltage-controlled variable frequency oscillator, and a mixer that receives the output signal of the mixer and the desired frequency f M via a low-pass filter. and means for applying the output signal of the phase detector to the voltage-controlled variable frequency oscillator via a filter. The frequency conversion circuit according to claim 1, which is a signal source whose output signal is the output of a voltage-controlled variable frequency oscillator. 3. The first signal source includes a variable frequency signal source, a third signal source, and a first signal source that receives output signals of the variable frequency signal source and the third signal source and generates an output signal.
the second signal source includes the variable frequency signal source, a fourth signal source that generates a signal with a frequency different from the output frequency of the third signal source by a desired frequency f M , and a fourth signal source that generates a signal with a frequency different from the output frequency of the third signal source by a desired frequency A variable signal source and a second mixer that receives the output signal of the fourth signal source and generates an output signal of a frequency that differs from the output frequency of the first mixer by the desired frequency f M. Frequency conversion circuit according to range 1. 4 The fourth signal source includes a mixer that receives the output signals of the third signal source and the voltage-controlled variable frequency oscillator, and a reference that generates the output signal of the mixer via a low-pass filter and the desired frequency f M The voltage controlled variable frequency oscillator comprises a phase lock loop consisting of a phase detector that receives an output signal from a signal source, and means for applying the output signal of the phase detector to the voltage controlled variable frequency oscillator via a filter. 4. The frequency conversion circuit according to claim 3, which is a signal source whose output signal is the output of a frequency oscillator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7099381A JPS57185707A (en) | 1981-05-12 | 1981-05-12 | Frequency conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7099381A JPS57185707A (en) | 1981-05-12 | 1981-05-12 | Frequency conversion circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57185707A JPS57185707A (en) | 1982-11-16 |
JPH0261803B2 true JPH0261803B2 (en) | 1990-12-21 |
Family
ID=13447573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7099381A Granted JPS57185707A (en) | 1981-05-12 | 1981-05-12 | Frequency conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57185707A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010500557A (en) * | 2006-08-07 | 2010-01-07 | 韓國電子通信研究院 | Circuit for continuously measuring discontinuous MIT of metal-insulator transition (MIT) element and MIT sensor using the circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5239305A (en) * | 1975-09-25 | 1977-03-26 | Hitachi Ltd | Code transmission system |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55162413U (en) * | 1979-05-11 | 1980-11-21 |
-
1981
- 1981-05-12 JP JP7099381A patent/JPS57185707A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5239305A (en) * | 1975-09-25 | 1977-03-26 | Hitachi Ltd | Code transmission system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010500557A (en) * | 2006-08-07 | 2010-01-07 | 韓國電子通信研究院 | Circuit for continuously measuring discontinuous MIT of metal-insulator transition (MIT) element and MIT sensor using the circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS57185707A (en) | 1982-11-16 |
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