JPH0256698B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Conventionally, when multiple CPUs each execute input/output instructions via a shared channel device, there is a period when exclusive control of the common area on main memory is incomplete. In some cases, startup information for channel devices was destroyed. Therefore, execute input/output instructions
Change control of the protection bit is performed so that the exclusive state of the main memory common area is continuously inherited from the CPU to the channel device.

[Industrial application field]

The present invention relates to an input/output instruction processing control method in a computer system having a plurality of central processing units and one or more channel devices, and particularly relates to an input/output instruction processing control method when an input/output instruction is executed by a plurality of central processing units. Concerning exclusive control of main memory common areas.

[Conventional technology]

FIG. 3 is a simplified example of a conventional computer system of the type to which the present invention relates.

In the figure, 30 to 33 are central processing units
CPU #0 to CPU #3, 34 are system control devices
SCU, 35 is the main memory unit MSU, 351 is the main memory common area, 352 is the protection bit, 36 is the channel device CHP, 361 is the microprocessor, 37
39 indicate I/O devices.

Each central processing unit CPU30 to 33 is connected to a channel device via a system control unit SCU34.
CHP36 and I/O devices 37 to 39
are shared.

The main storage MSU35 includes each central processing unit.
A main memory common area 351 that is commonly accessed by the CPUs 31 to 33 is provided, and when the central processing unit CPU executes an input/output command, information (or activation modification information) for starting the channel device CHP 36 is stored. written.

The main memory common area 351 is protected by a protection bit 352, and when the central processing units CPU30 to 33 or the channel device CHP36 respectively access the main memory common area 351,
By setting the protection bit 352 in the own device, access from other devices can be prohibited and exclusive control exclusive to the own device can be performed.

This protection bit 352 is composed of a plurality of bits, one bit corresponding to each device that can be an access source. A device attempting to use the main memory common area 351 turns on the bit corresponding to its own device.
and bits compatible with other devices.
By turning it off, the main memory common area 351
is locked to its own device, that is, an exclusive state is created.

By the way, when a certain central processing unit CPU writes activation information to the main memory common area 351 and then activates the channel device CHP, that central processing unit CPU stops using the main memory common area 351 and deprives it of its exclusive use. However, before the microprocessor 361 of the channel device CHP accepts this activation, other central processing units
When a CPU needs to access the same channel device CHP, since the exclusive state has already been released, there is a risk that the startup information written by the previous central processing unit CPU will be destroyed.

For this reason, as another conventional method, the central processing unit
When the CPU starts up the channel device CHP, the main memory common area 351 is not released from the exclusive state and the microprocessor 3 of the channel device CHP
When 61 recognizes the startup, it returns a startup confirmation (acknowledge) signal to the startup CPU, and
There is a device that releases the exclusive state when it identifies this startup confirmation signal. However, with this method, the CPU had to wait for a response signal from the CHP, resulting in a significant drop in CPU usage efficiency.

[Problem that the invention seeks to solve]

In the conventional input/output instruction processing method, the main memory common area is insufficiently protected at the cost of not reducing the utilization efficiency of the central processing unit, or else the main memory common area is sufficiently protected but the central The utilization efficiency of the processing equipment was either low or unsatisfactory in practice.

[Means for solving problems]

In order to solve the problems of the conventional method, in the process of the central processing unit activating a channel device in the main memory common area, the present invention transfers the exclusive state of the main memory common area from the central processing unit to the boot destination channel device. Set the protection bits to update so that
The boot destination channel device then accepts the boot while occupying the main memory common area, and after its microprocessor retrieves the necessary information from the main memory common area, it updates the protection bits and transfers the main memory common area. I am trying to release the exclusive status of the .

FIG. 1A is a conceptual diagram showing the basic configuration of the present invention.

In the figure, 10 to 13 are central processing units
CPU#0~CPU#3, 14 are system control devices
SCU, 15 is a main memory unit MSU, 151 is a main memory common area, 152 is a protection bit, 153 is boot information, 16 is a channel device CHP, and 161 is a microprocessor.

The operation will be described in accordance with the processing flow shown in FIG. 1B, taking as an example a case where one CPU #0 of the central processing unit executes an input/output instruction.

Since the central processing unit CPU#0 uses the main memory common area 151 of the main memory unit MSU via the system control unit SCU, the protection bit 152 is
Set the exclusive status of the own device.

Next, CPU #0 stores the main memory common area 151 as follows:
Write activation information for the channel device CHP16.

Next, CPU #0 transfers the contents of protection bit 152 from the exclusive state of CPU #0 to the channel device.
Change to exclusive status of CHP16.

Next, CPU #0 activates the channel device CHP16.

When the microprocessor 161 of the channel device CHP 16 identifies startup from CPU #0, it stores information necessary for execution in the main memory common area 151.
Import from.

Next, the microprocessor 161 updates the protection bit 152 in order to release the main memory common area 151 from being exclusive to its own device.

Next, the microprocessor 161 executes the contents of the specified input/output command.

[Operation] According to the present invention, one central processing unit exclusively uses the main memory common area to execute input/output commands, sets startup information, and then sends the information to the microprocessor of the channel device to be activated. Since there is no non-exclusive period during which other central processing units can access before control is transferred, there is no risk of the startup information set in the main memory common area being destroyed, and the central processing unit After setting the startup information in the common storage area, immediately rewrite the protection bits.
Since it is possible to move on to processing other instructions, high utilization efficiency can be obtained.

〔Example〕

FIG. 2A and FIG. 2B are configuration diagrams of a system according to an embodiment of the present invention, and the two figures can be used as one drawing by connecting them with a chain line.

In the figure, 20 to 23 are central processing units.
CPU#0~CPU#3, 24 are system control devices
SCU, 240 is MS access control unit, 241 is a group of prohibited gates, 242 is a coder, 243 is an OP valid register, 244 is a CPU machine number register, 2
45 is a multiplexer, 246 is a CPU bus register, 247 is a distributor, 25 is a main storage unit MSU,
251 and 252 are main memory common areas, 253 and 254 are protection bits, and 26 is a channel device.
CHU, 260 is MS access control unit, 261 is microprocessor, 262 is OP valid register, 263 is OP acknowledge register, 264
is a CPU machine number register, 265 is a CPU bus register, 266 is a distributor, and 267 is a group of area ID registers.

Each CPU#0 to CPU#3 is connected via SCU24.
Access MSU25 or CHU26.

When each CPU executes an input/output instruction, the SCU
MSU via the MS access control unit 240 of 24
Access the main memory common area corresponding to the boot destination channel device No. 25, set the protection bit to the exclusive state within the own device, write the boot information, and then rewrite the protection bit to the exclusive state of the boot destination channel device. .

For example, assuming that CPU #0 has completed the above operations, the CPU then sends an OP Valid (Operation Valid) signal to the channel device 26 via the SCU 24 to activate it. At the same time, the area ID information (identification information) of the main memory common area where the startup information was written earlier is sent via the CPU bus.
is sent to the CHU26.

This OP valid signal first passes through the inhibit gate group 241 of the SCU 24, is converted into a CPU machine number by the coder 242, and is sent to the OP valid register 243.
In addition to setting it to ON, the CPU machine number register 24
Set the CPU machine number (#0 in this case) to 4.

OP valid register 243 of SCU24 and
The contents of the CPU machine number register 244 are the same as those of the corresponding OP valid register 262 in the CHU 26.
It is transferred to the CPU machine number register 264.

The output of the OP valid register 262 is an OP acknowledge signal indicating a reception acknowledgment response from the channel device, and is applied to the distributor 247 of the SCU 24 via the OP acknowledge register 263.
Since the destination of the distributor 247 is selected by the CPU machine number (#0) output from the CPU machine number register 244, the OP acknowledge signal is sent to CPU #0.
will be returned to.

This frees up CPU #0 and allows it to move on to other processing.

On the other hand, the area ID information output from CPU #0 is sent to multiplexer 245 of SCU 24 and
It is transferred to the channel device 26 via the CPU bus register 246 and applied to the distributor 266 via the CPU bus register 265 of the CHU 26 .

When the OP variable is ON, the distributor 266
One area ID register corresponding to the CPU machine number is selected from the area ID register group 267, and the input area ID information is stored.

When the area ID information is set in the area ID register group 267, its valid flag V(a) turns ON, and the corresponding one of the prohibited gates in the prohibited gate group 241 of the SCU 24, that is, the prohibited gate connected to CPU #0. The gate becomes inhibited, and from then on, the OP valid signal from CPU #0 is not sent to the CHU 26 until the processing of CPU #0 is completed. However, other CPU#1~CPU#3
It is possible to start from.

The operations of the SCU 24 and CHU 26 described above are all executed by hardware circuits, so high-speed operations are possible.

In this way, the area ID information is passed to the microprocessor 261, and the microprocessor 26
1 reads necessary information from the corresponding main memory common area of the MSU 25 via the MS access control units 260 and 240, and further rewrites its protection bits to release the proprietary information.

Thereafter, the microprocessor 261 executes input/output control with the I/O device according to the read information.

〔Effect of the invention〕

As described above, according to the present invention, when a channel device is activated from a central processing unit, exclusive control of the main memory common area is completely performed, and there is no risk of redundant access by other central processing units. Furthermore, since the activated central processing unit is released without requiring a response from the channel device, the utilization efficiency of the central processing unit is greatly improved, and processing speed can be improved.

[Brief explanation of drawings]

FIG. 1A is a conceptual diagram showing the basic configuration of the present invention;
Figure 1B shows the processing flow, Figure 2A and 2
Figure B is a configuration diagram of a system according to one embodiment of the present invention;
The figure is a configuration diagram of a conventional system. In FIG. 1, 10 to 13...central processing unit
CPU, 14...System control unit SCU, 15...
...Main storage unit MSU, 151...Main memory common area,
152...Protection bit, 153...Startup information, 1
6...Channel device CHP, 161...Microprocessor.

Claims (1)

[Scope of Claims] 1. A main memory common area 151 that is provided with a plurality of central processing units 10 to 13, one or more processor control channel devices 16, and a main memory common area 151 accessed by each of these devices. In a computer system in which a protection bit 152 for exclusive control between devices is placed in 151, each of the plurality of central processing units 10 to 13 protects the main memory common area 151 when issuing an input/output command. After setting the exclusive state of the own device to the bit 152, write the startup information, and then change the contents of the protection bit 152 to the exclusive state of the processor control channel device 16 to be started, and then write the startup information to the bit 152. The processor control channel device 16 that is the startup destination recognizes the activation through the processor 161, and releases the exclusive state of the own device set in the protection bit 152 on the main memory common area 151. An input/output instruction processing method characterized by: