JPH0253962B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an automatic gain control circuit that prevents the level of an output signal from being fluctuated by a bias circuit.

[Technical background of the invention]

Generally, in signal processing circuits, an automatic gain control circuit (hereinafter referred to as
(abbreviated as AGC circuit) is provided. This AGC
For example, as shown in FIG. 4, the circuit includes a gain control amplifier 1, the output of this gain control amplifier 1, and a reference voltage.
A level comparator 2 that compares the output of the level comparator 2 with _E1 , an integral filter 3 that smoothes the output of the level comparator 2, and a control signal amplifier that amplifies the smoothed output of the comparator 2 and feeds it back to the gain control amplifier 1 as a control signal. It consists of 4.

In the circuit shown in FIG. 4, the signal input from the input terminal 5 is amplified by the gain control amplifier 1, and the signal is amplified by the output terminal 6.
The signal is output to the level comparator 2.
This output is at the reference level in level comparator 2.
E ₁ and the output level is compared to this reference level E ₁
When the value exceeds 1, a detection output is output, which is applied as a control voltage to the gain control amplifier 1 via the integral filter 3 and the control signal amplifier 4, and controls its gain to keep the output level constant. At this time, as shown in Figure 5, if the output DC level is E ₂ and the difference from the reference level E ₁ is ΔV (V), then theoretically the amplitude level of the output signal will be constant at 2ΔV (Vpp). .

[Problems with background technology]

The AGC circuit shown in Figure 4 operates as described above, but in the case of this circuit, the DC level of the output obtained at the output terminal 6 and the reference level are determined by completely separate bias circuits. The disadvantage is that the output level is directly affected by variations. To avoid this, it is possible to lead the output of gain control amplifier 1 to level comparator 2 through capacitive coupling, but if this AGC circuit is integrated, an external coupling capacitor may be required. There is a problem that the number of pins increases.

[Object of the Invention] The present invention has been made in response to the above-mentioned problems.The two outputs of a differential gain control amplifier are compared in level after having a certain level difference, and based on this comparison output, By configuring the gain control amplifier to control its gain, it is possible to suppress variations in the output signal level without adding a capacitive coupling capacitor, making it suitable for integrated circuits.
The purpose is to provide AGC circuits.

[Embodiments of the invention]

The AGC circuit of the present invention will be explained in detail below based on an example in which it is applied to a reproduced FM luminance signal processing circuit of a magnetic recording and reproducing apparatus.

FIG. 3 is a block diagram of a reproduced FM luminance signal processing circuit in a magnetic recording and reproducing apparatus, in which the video signal reproduced by the magnetic head 11 is transferred to the transformer 12.
After being amplified there, the luminance signal is extracted and guided to the AGC circuit 14 where the signal level is controlled to a predetermined value, and is further supplied to a dropout compensation circuit 15 and a limiter. is supplied to circuit 16. If a dropout occurs, it is corrected by a dropout compensation circuit 15, the amplitude level is adjusted to a constant level by a limiter circuit 16, and then demodulated by an FM demodulator 17 to produce a luminance signal.

FIG. 1 shows a specific circuit diagram of an embodiment of the AGC circuit according to the present invention.

The AGC circuit shown in Figure 1 consists of a gain control amplifier 2
1, level shift means 22, level comparator 23,
It has an integral filter 24 and a control signal amplifier 25.

The gain control amplifier 21 includes transistors Q ₁ , Q ₂ and transistors Q ₃ , which are configured in a double balanced differential type.
Two pairs of transistors Q ₄ , the collectors of which are connected to the emitter connection points of the transistors of each pair, and transistors Q ₅ and Q ₆ whose emitters are interconnected and connected to a reference potential point via a current source I ₁ . including. The base of transistor Q ₅ is connected to input terminal 25, and the base of transistor Q ₆ is connected to bias voltage source E ₁₀ . A bias voltage source E ₁₁ is connected to the bases of the transistors Q ₁ and Q ₄ .
The collector of transistor Q ₁ is connected to the power supply Vcc through resistor R ₁ together with the collector of transistor Q ₃ , and the collector of transistor Q ₂ is connected to the power supply Vcc together with the collector of transistor Q 3.
Together with the collector of Q ₄ , it is connected to the power supply Vcc through a resistor R ₂ .

The level shift means 22 has a base connected to the collectors of the transistors Q ₁ and Q ₃ of the gain control amplifier 21, an emitter connected to a reference potential point via resistors R ₃ and R ₄ and a current source I ₂ in series, and a collector. is the power
Transistor Q ₇ connected to Vcc, and transistors Q ₂ and Q ₄ whose bases are also the gain control amplifier 21
The transistor _Q8 has an emitter connected to a reference potential point via a resistor _R5 and a current source _I3 in series, and a collector connected to a power supply Vcc. Connection point of resistors R ₃ and R ₄ , resistor R ₅ and current source
The connection point of I ₃ is connected to the bases of transistors Q ₉ and Q ₁₀ , respectively, and to terminals 26 and 27, and an inductor L is connected between these terminals 26 and 27. The emitters of the transistors Q ₉ and Q ₁₀ are connected to a reference potential point and to output terminals 28 and 29 via resistors R ₆ and R ₇ , respectively.

The level comparator 23 has its base connected to the connection point between the resistor _R5 of the level shift means 22 and the current source _I3 , and its emitter connected to the reference potential point via the resistor _R8 .
A transistor whose collector is connected to the power supply Vcc
Similarly, the base of Q ₁₁ is connected to the connection point between the resistor R ₄ of the level shift means 22 and the current source I ₂ , the emitter is connected to the reference potential point via the resistor R ₉ , and the collector is connected to the power supply Vcc. transistor Q ₁₂ and
A transistor Q ₁₃ of a differential configuration, in _which each base is connected to the emitters of the transistors Q 11 and Q ₁₂ , and the emitters are connected to each other and connected to a reference potential point.
Has Q ₁₄ . The collector of transistor Q ₁₃ is connected to the power supply Vcc, the collector of transistor Q ₁₄ is connected to the power supply Vcc through a resistor R ₁₁ ,
The output of level comparator 23 is obtained from the collector of transistor _Q14 . This output is applied to the integral filter 24 via the terminal 31, and after being smoothed,
As a control signal amplified by the control signal amplifier 25,
It is supplied via terminal 32 to the base interconnection point of transistors Q ₂ , Q ₃ of gain control amplifier 21 .

The operation of the AGC circuit configured as above will be explained.

A signal supplied from the input terminal 30 is amplified by the gain control amplifier 21, and appears at the collectors of the transistors Q ₁ and Q ₃ and the collectors of the transistors Q ₂ and Q ₄ in opposite phases to each other. Both signals are applied to the bases of transistors Q ₇ and Q ₈ of level shifting means 22. Connection point of resistor R ₃ and resistor R ₄ , resistor R ₅ and current source
Since the inductor L is connected between the connection points with _I3 , signals having the same DC level and amplitude and opposite polarity appear at both connection points. One of these two signals is supplied as is to the base of the transistor Q ₁₁ of the level comparator 23, and the other is supplied to the base of the transistor Q 11 of the level comparator _23.
is supplied to the base of transistor _Q12 of level comparator 23 via. Here, the DC level of the other signal is shifted by ΔV (V) by resistor _R4 . In other words, the current value of current source I ₂ is
If i ₂ and the resistance value of resistor R ₄ are r ₄ , then ΔV=i ₂ · r ₄ . Therefore, the base potential of the transistor _Q11 changes as shown in FIG. 2a, and the base potential of the transistor _Q12 changes as shown in FIG.
The base potential of changes as shown in FIG. 2b.
When the amplitude levels of these two signals are 2ΔV (Vpp) or less, the base potential of transistor _Q11 is always higher than the base potential of transistor _Q12 . Therefore, the transistor Q ₁₄ is always non-conductive, the highest voltage signal is input to the control signal amplifier 25, and the level of the control signal is also the highest. Therefore, the gain of the gain control amplifier 21 increases, and the level of the output signal increases.
It increases towards 2ΔV (Vpp). When the amplitude level of two signals exceeds 2ΔV (Vpp), the transistor
Q ₁₄ conducts. This change in the collector potential of the transistor Q ₁₄ is smoothed by the integrating filter 24 and supplied to the base interconnection point of the transistors Q ₂ and Q ₃ of the gain control amplifier 21 via the control signal amplifier 25. By lowering the gain, the amplitude level of the output signal finally obtained at the output terminals 28 and 29 is reduced.
Fixed at 2ΔV (Vpp).

At this time, the inductor L connected between the terminals 26 and 27 functions as follows.

That is, in a circuit that demodulates an FM signal, a limiter is generally applied to the FM signal to make the amplitude constant before demodulating the signal. At this time, second-order distortion may occur in the limited signal, which may cause carrier leakage in the demodulator, or may be affected by sidebands of harmonic components of the second-order distortion. Various beat disturbances occur. For this reason, the level of second-order distortion is suppressed to -40dB or less. Furthermore, when a differential type limiter circuit is used, input offset causes second-order distortion, and it is necessary to prevent this.

Returning to Figure 1 again, due to the inductor L,
The base DC levels of transistors Q ₉ and Q ₈ are equal, and therefore the DC levels of their emitters are also equal, and this is supplied to a limiter circuit (not shown) via output terminals 28 and 29, so that a differential type limiter circuit can be used as a limiter circuit. It is possible to suppress the occurrence of second-order distortion even if a second-order distortion is used.

That is, the function of the inductor L is to equalize the DC level. Therefore, this can be eliminated if the DC level of the output of the gain control amplifier 21 has no variation and remains the same level. In that case, it is necessary to connect a resistor between resistor _R5 and current source _I3 . It goes without saying that if the values of current sources I ₂ and I ₃ are selected to be equal, the resistance values of resistors R ₃ and R ₅ are made equal, and the value of the newly added resistor is selected to be equal to that of resistor R ₄ . .

In any case, the amplitude level of the output signal is determined by the shift amount of the level shift stage.
Since the shift amount ΔV (V) is determined only by the current value of the current source I ₂ and the resistance value of the resistor R ₄ , there is almost no variation.

In the above description, an example has been described in which this invention is applied to a magnetic recording/reproducing apparatus, but this invention is not limited to the embodiment shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, one of the two output signals of the gain control amplifier configured as a differential amplification type is shifted by a certain level, the levels of both signals are compared, and the gain is adjusted according to the comparison output. By controlling the gain of the control amplifier, the amplitude level of the output signal can be set to a value determined by the shift amount, so it is possible to provide an AGC circuit with a stable output level.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing an automatic gain control circuit according to the present invention, Fig. 2 is a characteristic diagram for explaining the operation of Fig. 1, and Fig. 3 is a reproduction FM brightness signal processing circuit of a magnetic recording and reproducing device. Block diagram showing 4th
The figure shows a block diagram of a conventional automatic gain control circuit.
FIG. 5 is a characteristic diagram for explaining the operation of FIG. 4. 21... Gain control amplifier, 22... Level shift means, 23... Level comparator, 24... Integral filter,
25...Control signal amplifier.

Claims (1)

[Claims] 1. A differential gain control amplifier that amplifies an input signal and outputs two output signals with opposite phases to each other at the output terminal, and a level that shifts one of the two output signals by a certain level with respect to the other signal. a shift means, a level comparator for level-comparing the output signal of the level shift means and the other output signal, and converts the output of the level comparator into a DC signal and supplies it to the gain control amplifier as a gain control signal. An automatic gain control circuit comprising means.