JPH025289A - Dynamic RAM - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic RAM (Random Access Memory), and relates to a technique effective for use in, for example, a timing generation circuit thereof.

[Conventional technology]

Dynamic RAM uses an externally supplied address strobe signal as a reference and sequentially delays it to form various time-series operation timing signals necessary for the operation of row and column selection circuits. . In addition,
Regarding dynamic RAM, for example, Japanese Patent Application Laid-Open No. 1986-
No. 209397, regarding timing signal forming circuits, see, for example, "IEE Journal of Solid State Circuits" dated October 1980.
E E JOURNAL OF 5OLID-5T
ATE (:IRCUITS) J Vol, 5C-
15tlh5, page 844, etc.

(Problems to be Solved by the Invention) Elements made up of semiconductor integrated circuits have relatively large process variations.Therefore, conventional timing generation circuits are affected by the process variations of the elements, and the process variations are relatively large.
Even in the designed RAM, one chip has a long delay time, resulting in a slow access time, while another chip has a small delay time, resulting in a loss of operating margin and is therefore considered defective. Therefore, in the conventional dynamic RAM, it is necessary to design circuit constants that take the above-mentioned process variations into account, and the operating speed is sacrificed accordingly. Chips that exceed the predicted process variation are determined to be defective chips.

An object of the present invention is to provide a dynamic RAM that achieves high yield while increasing speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a function is added to the timing generation circuit that forms time-series timing signals for memory access, using fuse means that is selectively disconnected to lengthen the delay time. do.

[For production]

According to the above-mentioned means, the delay time of the timing generation circuit is set to the minimum necessary, and a chip in which an operating margin defect has occurred can be repaired by increasing the delay time. It can achieve high speed and high yield.

〔Example〕

FIG. 3 shows a dynamic RA to which this invention is applied.
, M is shown. The example circuit shown in the figure is an i G F E T (i n5 ulated G
ate Field Effect Transis
tor), and is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon, using known semiconductor S integrated circuit manufacturing techniques.

The memory array MIL includes a plurality of complementary data blocks DL and DI.
, , consists of a plurality of word lines WL and a plurality of Guinami Fuku type memory cells MC. The memory array MIL is of a folded bit line (digit line or data vA) type. Therefore, memory cell MC is arranged at one of two intersections formed by one complementary data line and one word line. Sense amplifier SA as described later
The memory array MIR arranged on the right side with J interposed therebetween has the same configuration as the memory array MIL described above.

As shown in the representative example, a 1-bit memory cell MC consists of an information storage capacitor Cs and an address selection MO3FETQm, and has a logic "1" ll.
Information on Q* is stored in the form of whether or not there is a charge on the capacitor Cs. To read information, turn on the MO3FETQm, couple the capacitor Cs to one of the complementary data lines, and sense how the potential of the data line changes depending on the amount of charge stored in the capacitor Cs. carried out by.

In each of memory arrays MIL and MIR, memory cells MC are formed small as described above, and many memory cells are coupled to complementary data lines arranged in parallel. Therefore, the ratio between the capacitor Cs and the stray capacitance Co (not shown) of the data line DL becomes a very small value.

Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs is a very small signal. However, in this embodiment, by adopting the shared sense method in which the data line is divided into left and right parts with the sense amplifier SAI in between as described above, the length of one data line and the number of connected memory cells can be halved. Therefore, the stray capacitance Co (not shown) of the data line is reduced.

As a result, the level of the read signal from the memory cell appearing on the data line can be made relatively thick.

A dummy cell DC is provided as a circuit that forms a reference potential for the sensing operation of the sense amplifier SAI that detects such a minute signal.

This dummy cell DC is manufactured under the same manufacturing conditions as the memory cell MC. Switch MO3FETQd made with the same design constants
and a capacitor Cd having a capacitance value approximately half that of the capacitor Cs. The capacitor Cd of this dummy cell DC is a reset MO during standby.
The ground potential of the circuit is stored by 3FETQd'.

The sense amplifier SAI is composed of a plurality of unit circuits such as amplifying MO3FETs Q1 and Q2 in a latch format, which are shown as a representative example. This sense amplifier SAI uses a timing signal (
The sense amplifier control signal) is expanded to a sensing period determined by φpal +φpa2.

One unit circuit (Ql) of sense amplifier SAI.

Q2) is a pair of complementary data lines DL whose input/output terminals are arranged in parallel on the memory array MIL side as shown in the figure;
Switch MO3FETQ3. A switch M is connected to a pair of complementary data lines DL and DL connected through Q4 and arranged in parallel on the side of the memory array MIR.
They are coupled via O3FETQ11, Ql2.

The above switch MO3FETQ3. Q4 outputs the timing signal SHL when the memory array MIL is in the selected state.
is maintained in the on state. Above switch MO3FE
TQI 1. Ql2 is maintained in the on state by the timing signal SHR when the memory array MIR is placed in the selected state.

The number of memory cells coupled to each of the divided left and right complementary data lines is made equal to each other in order to improve detection accuracy. One dummy cell D is connected to each pair of input/output nodes of the unit circuit of sense amplifier SA1.
C is connected.

In the above addressing, when the memory cell MC coupled to one of the pair of complementary data lines of the memory array MIL or MIR is selected, one data line of the pair of input/output nodes of the unit circuit of the sense amplifier SAI is selected. One of the pair of dummy word lines DWL, DWL is selected so that the dummy cell DC coupled to one human output node coupled via the switch MOS FET is selected.

The unit circuit of the sense amplifier SAI is composed of a pair of cross-connected MOSFETs Q1 and Q2 as described above, and their positive feedback action differentially amplifies minute signals appearing between complementary data lines. do. This positive feedback operation is performed by MOSFETQ2 by timing signal φpal.
7 is turned on. This MOS
FETQ 27 is adapted to exhibit a relatively small conductance when it is made conductive. The sense amplifier S
When the AI starts operating, the potential difference previously applied between the complementary data lines is amplified by addressing. That is, the higher data line potential is lowered at a slower rate, and the lower data line potential is lowered at a faster rate. Then, the MOS FETQ28 is made conductive by the timing signal φpa2 generated at the timing when the voltage difference becomes large to a certain extent. M
OSFET Q28 is configured to have a relatively large conductance when it is turned on. MOSFE
When TQ2B starts conducting, the lower data line potential is rapidly lowered. By operating the sense amplifier SAI in two stages in this way, a significant drop in the higher potential is prevented. In this way, when the lower potential drops below the threshold voltage of the cross-coupled MOSFET, the positive feedback operation ends, and the higher potential drops while remaining at a potential lower than the power supply voltage Vcc and higher than the threshold voltage. , the lower potential finally reaches the ground potential (0■).

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high level or low level potential obtained by this sensing operation. However, as mentioned above, if the high level drops to a certain level or more with respect to the power supply voltage Vcc, a malfunction occurs that is read as logic '0'' after reading and rewriting several times. However, an active restore circuit is provided to prevent this malfunction.

This active restore circuit has the function of selectively boosting only high level signals to the potential of power supply voltage Vcc without giving any effect to low level signals.

In each memory array, a non-ignorable coupling capacitance is formed between each data line and each word line. Therefore, when the level of one word line is changed, undesired potential fluctuations that are essentially considered as noise are imparted to each data line. However, in a folded bit line memory array, each word line WL crosses both complementary data lines. Therefore, Ward & IWL
Noise that is applied to the complementary data line in response to level changes is considered common mode noise. The differential sense amplifier SAI is substantially insensitive to such common mode noise.

Precharge circuits PCLI and PCRI are provided for both memory arrays MIL and MIR, respectively. That is, in memory array MIL, as shown by way of example as a representative unit circuit, precharge MO3FETs Q30 . Consists of Q31. Other complementary data lines are also provided with unit circuits PC made of precharge MO3FETs similar to those described above.

These precharge circuits PCIL are controlled by a precharge pulse PCL. In the memory array MIR, MO3F as exemplified as above
ETQ32. Precharge MOS F consisting of Q33
ET will be provided. Other complementary data lines are also provided with unit circuits PC made of precharge MO3FETs similar to those described above. These precharge circuits PCIR are controlled by a precharge pulse PCR.

The rough operation of the above precharge MO3FET is RA
During M non-access periods, that is, when a row address strobe signal RAS (not shown) is at a high level, it is set at a high level accordingly. As a result, each complementary data line is precharged to a high level close to the level of power supply voltage Vcc. Precharge signal P
Of CL and PCR, the signal PCL or PCR corresponding to the side of the memory array MIL or MIR where the memory cell to be selected exists is set to a low level in response to the start of RAM access, and is set to the non-selected side. The signal corresponding to the memory array MIL or MIR is kept at high level. In other words, the precharge operation continues to be performed on the unselected memory array MIL or MIR. By doing this, the precharge operation is repeated on the non-selected complementary data line, so that the complementary data line in the non-selected state is connected to the complementary gate line in the non-selected state by parasitic capacitance, and other signal lines such as column selection lines are connected to the complementary data line in the non-selected state. Undesirable level fluctuations due to coupling noise can be prevented.

Each unit circuit in the precharge circuits PCIL and PCIR may include an equalizing MO3FET that shorts complementary data lines together in response to precharge timing signals PCL and PCR.

In the same figure, the input/output nodes of one unit circuit forming the sense amplifier SAI are MO3FETQI 9. forming the column switch circuit. MO3FETs Q21 . Q2
2 via common complementary data &%CD2. Connected to CD2. Each of the other unit circuits is a similar MO3FETQ
23°Q24 and Q25. Q26 to the respective common complementary data line pairs CDI, CDI and CD2 . Connected to CD2.

In this way, two sets of common complementary data lines CDI, CDi and CD2 . By providing CD2, column switch M
The gates of O3FETQI9 to Q22 are shared.

This common gate is supplied with a data line selection signal Y1 formed by a unit circuit forming a column address decoder. As a result, unit circuits constituting columns and address decoders can be wired at the pitch of a total of four data lines, and by matching the pitch of both, unnecessary space is not created on the semiconductor substrate. can.

Although not shown in the drawings, the RAM of this embodiment has a so-called 4-mat configuration in which memory arrays MIL and MIR similar to the memory arrays MIL are arranged on the left side of the memory array MIL, although this is not particularly limited. The above column selection signal Y1
etc. are the column selection MOs of the memory array (not shown).
It is also commonly supplied to the gates of 3FETs. Therefore, the column selection lines extend toward these memory arrays. This allows memory cells consisting of a total of 4 bits to be selected at the same time. Such an address selection method can easily cope with a nibble mode, such as reading out 4-bit data serially, by relatively simple circuit modification of the selection circuit and the like.

Although not particularly limited, the RAM of this embodiment is of a multi-address type in which address signals are supplied from a common external terminal.

It is also used in an address buffer that receives an address signal from an external terminal and supplies an internal address signal to the address decoder, and a timing control circuit that forms various timing signals necessary for the operation of internal circuits according to control signals from an external terminal. The timing generation circuit shown in FIG. 1 is composed of a circuit as described below.

FIG. 1 shows a circuit diagram of an embodiment of a timing generation circuit that is generated in a time-series manner in the dynamic RAM. Although the circuit symbols attached to the MOSFETs in the figure are the same as those in the circuit diagram in Figure 3 above, it should be understood that the MOSFETs have different circuit functions.

The timing generation circuit TGI shown in the figure is composed of the following circuit elements. MO3FETQI on the power supply voltage side receiving the input timing signal φi, MO3FETQ2 on the ground potential side receiving the precharge signal φ1, and the above MOS F
MO3FETQ4, which receives the output signal obtained from the connection point of ETQ1 and Q2, and precharge MO3FETQ3, which receives precharge signal φ2 and is provided at the drain of MO3FETQ4, constitute a delay circuit for the input timing signal φi. .

The drain output of the MO3FETQ4 is the ground potential side output MO3FETQI1. Applied to the gate of Ql 3. The input timing signal φi is the transmission game 1-M
It is supplied to one electrode of the capacitor (bootstrap capacitance) CB through the 03FETQ7. MO3FB above
A cutting MO3FET Q5 to which a power supply voltage Vcc is constantly applied to its gate is provided between the gate of TQ7 and the drain of the MO3FET Q4. In addition, the gate of the transmission gate MOSFET Q7 and the power supply voltage ■c
A precharge MO3FETQ6 receiving the second precharge signal φ2 is provided between the second precharge signal φ2 and the second precharge signal φ2. The reason for this is to prevent the high voltage extraction current generated by the bootstrap capacitor CB from flowing back to the input terminal side via the transmission gate MO3FETQ7 during a reset operation to be described later. That is, the reset MO3FET Q8 is turned on by the precharge signal φ1 rising at a relatively early timing, and its extraction is performed. By doing so, it is possible to prevent the characteristics from deteriorating due to bidirectional current flowing through the MO3FET Q7. In this way, the precharge signals φ1 and φ2 are applied to the MOSFETQ
This is formed in order to prevent deterioration of the characteristics of 7.

The gates of the output MO3FETs QIO and Q12 on the power supply voltage Vcc side are connected to one electrode of the capacitor CB. This MO3FETQIO and the above MO3FETQI
The other electrode of the capacitor CB is connected to the connection point with the capacitor CB. A reset MO3FET Q9 receiving the precharge signal φ1 is provided between one electrode of the capacitor CB and the ground potential point of the circuit. Above output M
Between the gate of O3FET QIO, Q12 (one electrode of bootstrap capacitor CB) and the ground potential point of the circuit, there is a reset MO3 which receives the precharge signal φ1.
FETQ8 is provided. And the above output MOSFE
Output timing signal φ0 is sent from the connection point between TQI 2 and output MO3FETQ13.

The operation of the timing generation circuit TGI is as follows. After the precharge signals φ1 and φ2 have been changed from high level to low level, in response to input timing signal φi rising to high level, MO3FETQ1 turns on, and its conductance and MO3FETQ4
According to the time constant with the parasitic capacitance consisting of the gate capacitance, etc.,
During the precharge period, the gate voltage of the MO3FETQ4, which has been set to the ground potential due to the high level of the precharge signal φ1, is raised to a high level. When MOSFET Q4 is turned on in response to the rise of this gate voltage, the potential of node A, which has been precharged to high level by the high level of precharge signal φ2 during the precharge period, is pulled out from high level to low level. form a delayed signal that changes to

During the precharge period, the precharge signal φ2
Due to the high level of , the gate of MO3FETQ7 is precharged to high level. Therefore, MO3F
ETQ7 is turned on. Precharge signal φ
The capacitor CB is reset by the high level of 1. Then, the high level signal of the timing signal φi is supplied to one electrode of the capacitor CB through the MO3FET Q7 in the on state. At this time, if the potential of node A is still at high level, MO3FETQI
Since I and Q13 are turned on, capacitor C
B is charged up. MO3FETQ according to the charge up of 7 to capacitor CB like this
I01Q12 turns on, but MO3FETQI
O and Q12! :For MO3FETQI 1 and Q1
3 has a large conductance (as it is set, the output voltage determined by the respective conductance ratio remains at a low level close to the ground potential. In the charge-up operation to the above-mentioned capacitor CB, MO5FETQ
7 is self-bootstrapped by the gate capacitance between the gate and the channel, increasing the gate voltage, so that the high level of the timing signal φi is transmitted to the capacitor CB without any level loss. The bootstrap voltage of this MO3FETQ7 is the transmission gate MO3FETQ5
is turned off, so it does not leak to the node A side.

When the level of the output A of the delay circuit changes to high level or low level, the MO3FET that was in the on state
QI 1 and Q12 are turned off from the on state. As a result, a high level due to the ON state of the MOS FETQlo is transmitted to the electrode of the capacitor CB, which has been set to the ground potential, and a bootstrap is applied, resulting in a voltage higher than the power supply voltage cc. At this time, since the MO3FET Q7 is turned off by the low level of the node A, the bootstrap voltage formed by the capacitor CB does not leak to the input timing signal φi side, and the desired boost is achieved. This results in high voltage. Since the output M'0SFETQ12 will be supplied with a high voltage boosted above the power supply voltage Vcc, the level of the output timing signal φ0 output from its source should be set to a high level like the power supply voltage Vcc. I can do it. From this, the timing generation circuit T
GI receives input timing signal φi and outputs output timing signal φ0 with a delay time set by the delay circuit.

For example, the timing signal φ0 is a timing signal φ×'' that forms the word line selection timing signal φX as shown in FIG. memory cell MC like
In other words, in order to prevent the level of the high-level signal transmitted to the information storage capacitor Cs from decreasing due to the threshold voltage of the address selection MOSFET Qm, be made expensive. Such boosted word line selection timing signal φX is, for example, the timing signal φX
It can be formed by charging up the bootstrap capacitance with 0 and driving the bootstrap capacitance with the delayed signal.

Output timing signal φ of the above timing generation circuit TGI
0 is used as the input timing signal φi' of the timing generation circuit TG20 on the other hand. The timing generation circuit TG2 forms, for example, an operation timing signal φpal for the sense amplifier.

The timing generation circuit TG2 is constituted by a circuit similar to the timing ordering circuit TGI. However, as shown in the waveform diagram of FIG. 2, the word line selection timing signal φ
In other words, the word line is selected and the signal Vs read from the memory cell MC is placed on the complementary data line DL or DL at the desired level so that the timing signal φpal has a time difference with respect to X. MO configures a delay circuit to activate the sense amplifier after waiting for
The constant of SFET can be determined.

In this example, due to process variations in element constants,
In order to relieve the malfunction caused by the timing signal φpal that activates the sense amplifier being generated before the delay time becomes shorter and the signal Vs reaches the desired level, the input side of the timing generation circuit TG2 is A resistor R constituting a delay circuit is provided. This resistance R
Fuse means F are provided at both ends of the circuit to short-circuit them. This fuse means is not particularly limited.

It consists of extremely thin wiring made of the second aluminum layer, and can be cut by laser beam irradiation. Therefore, when the semiconductor wafer is completed, the resistor R is short-circuited by the fuse means, and the timing signal φp]1 (formed by the timing generating circuit TG2)
This is determined by the element constant of the FET.

In semiconductor wafer probing, if it is determined that the sense amplifier is malfunctioning, the fuse means is cut by irradiation with the laser beam. As a result, the input timing signal φi', which serves as a reference for the operation of the timing generating circuit TG2, rises from a low level to a high level with a delay of the delay time formed by the resistor R and the parasitic capacitance in its wiring. As a result, the timing at which the operation timing signal φpal of the sense amplifier formed in the timing generation circuit TG2 is generated is as follows.
This results in a delay with respect to the word line selection timing signal φX. As a result, the time required to read stored information from the memory cells is lengthened, so that the signal level of the signal Vs read to the complementary data lines DL and DL increases, making it possible to relieve malfunctions caused by insufficient levels as described above. can. This means that the word line selection timing signal φX and the sense amplifier operation timing signal φpa
In addition to the time difference (delay time) between sense amplifier timing signals φpal and φpa2, other representative selection timings for the row system include the operation timing signal of the row address parallel rough and the word line. There is a time difference with the selection timing signal, and a time difference between the operation timing signal of the sense amplifier and the timing signal of the active restore circuit. Typical selection timing signals for the column system include the time difference between the address buffer and the column selection timing signal φy, and the time difference between the column selection timing signal φy and the main amplifier operation timing signal φ1II.
a, the main amplifier operation timing signal φf
There is a time difference between fIa and the operation timing signal φop of the output buffer.

By lengthening each of these time differences as necessary by providing the delay resistor and fuse means as described above, defects caused by insufficient operating margin can be relieved.

Therefore, in this embodiment, the delay time set by the delay circuit including MOSFET Cl or Q4 provided in each of the timing generation circuits can be designed to be as short as possible.

This makes it possible to access the RAM at high speed since there is no need to set a time margin longer than necessary in consideration of yield, as is the case in the past. Then, for chips where the time set by the delay circuit does not have enough operating margin due to process variations, the delay time can be extended by cutting off the fuse means, making it possible to remedy malfunctions. Therefore, the yield can be increased.

The effects obtained from the above examples are as follows. That is, (1) It is possible to lengthen the delay time by using fuse means that is selectively disconnected for a timing generation circuit that forms a time-series timing signal for memory access. By adding this function, it is possible to set the delay time of the delay circuit provided in the timing generation circuit to the necessary minimum value, thereby achieving the effect of enabling high-speed access.

(2) According to (1) above, the delay time can be increased by cutting the fuse means for a chip whose operating margin is insufficient due to process variations during the time set by the delay circuit; It is possible to repair malfunctions, and the yield can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, the delay time adjustment resistor R may be provided at the gate or drain output of MO3FETQ4. Furthermore, a plurality of delay time resistors may be provided for one timing generation circuit to enable delay adjustment in a plurality of stages. In addition to using a polysilicon layer, the delay resistor may be a MOS F E that is constantly turned on.
Various embodiments can be taken, such as one using T.

Further, as the fuse means, in addition to cutting by irradiation with a laser beam, a method using a polysilicon layer and cutting by passing a current through it may be used. Furthermore, even when the timing generation circuit is composed of an 0M03 circuit, the delay time can be adjusted using the resistor and fuse means as described above.

The precharge level of the complementary data line is the power supply voltage VCC.
It is also possible to adopt a half precharge method in which the precharge is 1/2. In this case, by making the capacitance value of the capacitor CB have a large ratio to the load capacitance of the signal line, an intermediate level that turns off the precharge MO3FET and the transmission gate MOS FET that divides the complementary data line is set. All you have to do is make it happen. Note that in this case, the dummy cell for forming the reference potential of the sense amplifier can be omitted. Further, the precharge level of the complementary data line may be set to a predetermined potential other than the above-mentioned power supply voltage VCC or intermediate potential Vcc/2.

In the dynamic RAM, row-related and column-related address signals may be supplied from independent external terminals. In this case, a series of time-series timing signals necessary for the operation of the row-related and column-related selection circuits are formed using the low level of the chip selection signal or the like as a reference.

The present invention can be used not only for a general-purpose dynamic RAM but also for a RAM for specific applications such as an image memory using dynamic memory cells.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, a function is added to the timing generation circuit that forms time-series timing signals for memory access, using fuse means that is selectively disconnected to lengthen the delay time. By doing this, the delay time of the delay circuit provided in the timing generation circuit can be set to the minimum necessary, so high-speed access is possible. By lengthening the delay time by cutting off the means, malfunctions can be repaired, and the yield can be increased.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a timing generation circuit according to the present invention, FIG. 2 is a waveform diagram for explaining an example of a RAM operation timing signal, and FIG. 3 is a circuit diagram to which the present invention is applied. Guinami-soku type RAM
FIG. 2 is a circuit diagram of main parts showing an embodiment of the present invention.

Claims (1)

Claims: 1. A dynamic RAM characterized by including a timing generation circuit that makes it possible to lengthen the delay time of a delay circuit by using fuse means that is selectively blown. 2. The above-mentioned fuse means is provided at both ends of a resistance element inserted in series in the signal transmission path, and when the fuse means is cut, the resistance means is inserted into the signal transmission path. Dynamic RAM described in Section 1
. 3. The dynamic RAM according to claim 1 or 2, wherein the fuse means is selectively cut by irradiation with a laser beam.