[go: up one dir, main page]

JPH0251251A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH0251251A
JPH0251251A JP20195388A JP20195388A JPH0251251A JP H0251251 A JPH0251251 A JP H0251251A JP 20195388 A JP20195388 A JP 20195388A JP 20195388 A JP20195388 A JP 20195388A JP H0251251 A JPH0251251 A JP H0251251A
Authority
JP
Japan
Prior art keywords
circuits
ground
circuit
substrate
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20195388A
Other languages
Japanese (ja)
Inventor
Hiroichi Ishida
博一 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20195388A priority Critical patent/JPH0251251A/en
Publication of JPH0251251A publication Critical patent/JPH0251251A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To being the parasitic capacity and the resistance between a plurality of circuits and a substrate in accordance with each other by floating the ground lines of a plurality of circuits from a substrate ground and connecting the ground line of the other circuit than said plurality of circuits with the substrate ground. CONSTITUTION:Connecting the ground line of a circuit C, the other circuit than circuits A and B which are required to have the same characteristic, to a substrate ground at a ground point 20 and floating the ground lines of the circuits A and B, which are required to have the same characteristic, from the substrate ground, the ground of a signal leaking through a parasitic element is connected to the grounds of the circuits A and B in a low-impedance circuit outside the integrated circuit to make the effect of the parasitic element equal to the circuit A and the circuit B and no difference in characteristic between the circuits A and B is exhibited. Thereby the characteristics of a plurality of circuits are placed in accordance with each other.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、同一特性が要求される複数の回路が同一基
板上に設けられている半導体集積回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit in which a plurality of circuits requiring the same characteristics are provided on the same substrate.

〔従来の技術〕[Conventional technology]

第4図は従来のこの種の半導体集積回路を示す平面図で
あり、図において、A、Bは、同一特性が要求されるミ
クサ回路、高周波増幅回路、周波数弁別回路等の各回路
ブロックを一系列として成る回路、Cは回路A、Bを制
御する制御回路または回路A、Bに直接関係しない回路
または回路A。
FIG. 4 is a plan view showing a conventional semiconductor integrated circuit of this type. In the figure, A and B indicate circuit blocks such as a mixer circuit, a high frequency amplification circuit, and a frequency discriminator circuit that are required to have the same characteristics. C is a control circuit that controls circuits A and B, or a circuit or circuit A that is not directly related to circuits A and B.

Bのどちらにも同じ割合で関係する回路等からなる他の
回路、1はこれら回路A、B及び他の回路Cからなる半
導体集積回路、2,3・・・8・・・10・・・12・
・・15・・・18.19はポインティングバット。
1 is a semiconductor integrated circuit consisting of these circuits A, B and another circuit C; 2, 3...8...10... 12・
...15...18.19 is a pointing bat.

20は半導体基板1へのアース点である。20 is a ground point to the semiconductor substrate 1.

第5図は基板アースの例を示すバイポーラ集積回路より
なる半導体集積回路の断面図であり、図において、21
は基板アースへのアルミ配線、22はコレクタ電極のア
ルミ配線、23はベース電極のアルミ配線、24はエミ
ッタ電極のアルミ配線、25はエミツタ層、26はベー
ス層、27はコレクタ層、28はフローティングコレク
タ、29はP形の基板、30は酸化膜、31は分離層、
32〜39は寄生容量、40.41は寄生抵抗である。
FIG. 5 is a sectional view of a semiconductor integrated circuit made of a bipolar integrated circuit showing an example of substrate grounding.
is the aluminum wiring to the substrate ground, 22 is the collector electrode aluminum wiring, 23 is the base electrode aluminum wiring, 24 is the emitter electrode aluminum wiring, 25 is the emitter layer, 26 is the base layer, 27 is the collector layer, 28 is floating Collector, 29 is a P-type substrate, 30 is an oxide film, 31 is a separation layer,
32 to 39 are parasitic capacitances, and 40.41 is a parasitic resistance.

次に動作について説明する0回路Bの基準がアース電位
またはある固定電位であって(第5図はP基板の場合を
示し、該基板をアース電位にした場合を示すが、N基板
の場合はP基板の場合と異なる。)、この基準点が基板
アースへのアルミ配$I21に接続されていると1回路
Bのアースへの電流の一部が、基板アースへのアルミ配
線21゜分離層31、基板29を通して外部に引き出さ
れ、この間の抵抗等により、基板29がアースから浮き
1回路Bへ容量結合、電流・電圧リーク等で影響を及ぼ
すため1回路Aと回路Bが同一であっても、厳密には特
性が一致しない、精度の要求される回路では、この点で
特性が一致せず問題である。
Next, the reference of the 0 circuit B whose operation will be explained is earth potential or a certain fixed potential (Figure 5 shows the case of a P board, and shows the case where the board is set to the ground potential, but in the case of an N board, ), if this reference point is connected to the aluminum wiring $I21 to the board ground, a part of the current to the ground of circuit B will be transferred to the aluminum wiring 21° separation layer to the board ground. 31. It is drawn out through the board 29, and due to the resistance etc. in between, the board 29 floats from the ground and affects 1 circuit B through capacitive coupling, current/voltage leakage, etc., so 1 circuit A and circuit B are the same. However, in circuits that require precision, the characteristics do not strictly match, and this is a problem as the characteristics do not match.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体集積回路は以上のように構成されているの
で、回路A、Bの動作時、これら回路A。
Since the conventional semiconductor integrated circuit is configured as described above, when circuits A and B operate, these circuits A and B operate.

Bの動作信号の一部が、寄生容量32〜39、寄生抵抗
40.41等の寄生素子を通して漏れ信号として基板2
9上に乗り、この場合、例えば、回路A、Bのうちの一
方のアースが基板29に接続されていると、前述した寄
生素子を通して漏れ信号が基板アースへのアルミ配線2
1、分離層31゜基板29を通して外部へ取り出され、
集積回路外で回路A、Bのうちの他方のアースと接続さ
れることから、基板アースへ接続した側の回路が寄生素
子の影響で電位が上がり回路A、Bが同一回路であって
も同一の性能を得ることができないと言う問題点があっ
た。
A part of the operation signal of B is transmitted to the substrate 2 as a leakage signal through parasitic elements such as parasitic capacitances 32 to 39 and parasitic resistances 40 and 41.
In this case, for example, if the ground of one of the circuits A and B is connected to the board 29, a leakage signal will pass through the above-mentioned parasitic element to the aluminum wiring 2 to the board ground.
1. The separation layer 31° is taken out to the outside through the substrate 29,
Since it is connected to the ground of the other of circuits A and B outside the integrated circuit, the potential of the circuit connected to the board ground increases due to the influence of parasitic elements, even if circuits A and B are the same circuit. There was a problem in that it was not possible to obtain the performance of

この発明は上記のような問題点を解消するためになされ
たもので、同一特性を要求される複数の回路の特性を一
致させることができる半導体集積回路を得ることを目的
とする。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor integrated circuit that can match the characteristics of a plurality of circuits that are required to have the same characteristics.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体集積回路は、同一基板に設けられ
た同一特性が要求される複数の回路とこの複数の回路以
外の他の回路のうち、上記複数の回路はそのアースライ
ンを基板アースがら浮かせ、他の回路はそのアースライ
ンを基板アースに接続したものである。
In the semiconductor integrated circuit according to the present invention, among a plurality of circuits provided on the same substrate that require the same characteristics and other circuits other than the plurality of circuits, the plurality of circuits have their ground lines floating from the substrate ground. , and other circuits have their ground lines connected to the board ground.

〔作用〕[Effect]

この発明における半導体集積回路は、同一特性を要求す
る複数の回路のアースラインを基板アースから浮かせ、
他の回路のアースラインを基板アースに接続することに
より、同一特性を有する複数の回路の基板アースからの
影響を等しくした。
In the semiconductor integrated circuit according to the present invention, the ground lines of a plurality of circuits that require the same characteristics are floated from the substrate ground,
By connecting the ground lines of other circuits to the board ground, the influence from the board ground on multiple circuits having the same characteristics was equalized.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図において、前述した従来技術を示す第4図と対応する
部分には同一符号をつけて示している。この実施例の半
導体集積回路において、同一特性が要求される回路A、
Bのアースラインが基板アースから浮かされ、これら回
路A、B以外の他の回路Cのアースラインがアース点2
0で基板アースに接続されている。
An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, parts corresponding to those in FIG. 4 showing the prior art described above are designated by the same reference numerals. In the semiconductor integrated circuit of this embodiment, a circuit A that requires the same characteristics,
The ground line of B is lifted from the board ground, and the ground line of circuit C other than these circuits A and B is connected to ground point 2.
0 and is connected to the board ground.

次に動作について説明する。従来の技術の欄で説明した
ように回路A、Bの動作時に信号の一部が、寄生素子を
通して基板29に乗るので、同一特性が要求される回路
A、B以外の他の回路Cのアースラインを基板アースに
接続し、同一特性が要求される回路A、Bのアースライ
ンを基板アースから浮かせることにより、寄生素子を通
して漏れた信号のアースは、集積回路外の低インピーダ
ンス回路で回路A、Bのアースと接続されることになり
5寄生素子による影響は回路A、Bに対して等しくなり
1回路A、Bの特性差が出ない。
Next, the operation will be explained. As explained in the prior art section, when circuits A and B operate, a part of the signal is transferred to the substrate 29 through parasitic elements. By connecting the line to the board ground and floating the ground lines of circuits A and B, which require the same characteristics, from the board ground, the ground of the signal leaked through the parasitic element can be grounded by a low impedance circuit outside the integrated circuit. Since it is connected to the ground of circuit B, the influence of the five parasitic elements is the same on circuits A and B, and there is no difference in characteristics between circuits A and B.

なお、第1図は基本的なアースの取り方のみについて述
べたが、第2図に示すように回路Aと回路Bとを半導体
チップ上のXl−X2に垂直な面に対して面対称にする
と、回路Aと回路Bがらアース(基板29)への寄生容
量・抵抗が同一になり、第1図のものに比べ、より回路
A、Bの特性が一致する。この場合、回路A、B内の各
回路E〜Hを構成するダイオード、抵抗、トランジスタ
の方向は、配置・配線がほぼ等しくされている。
Although Figure 1 describes only the basic method of grounding, as shown in Figure 2, circuit A and circuit B can be arranged symmetrically with respect to the plane perpendicular to Xl-X2 on the semiconductor chip. Then, the parasitic capacitance and resistance of circuit A and circuit B to the ground (substrate 29) become the same, and the characteristics of circuits A and B match more closely than in the case of FIG. 1. In this case, the directions of the diodes, resistors, and transistors constituting each of the circuits E to H in the circuits A and B are arranged and wired in substantially the same direction.

この第2図は回路A、Bとポンディングパッド間も同一
の例であるが、第3図はXl−X2に対し左右にシフト
した形で面対称にした例を示したものである。
Although FIG. 2 shows an example in which the circuits A and B and the bonding pads are the same, FIG. 3 shows an example in which the circuits are shifted left and right with respect to Xl-X2 to make them plane symmetrical.

尚、上記実施例では同一特性が要求される複数の回路の
数をA、Bの2個としたが、勿論、3個以上であっても
よい。
In the above embodiment, the number of circuits required to have the same characteristics is two, A and B, but of course the number may be three or more.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、特性を一致させよう
とする複数の回路のアースラインを基板アースから浮か
せ、この複数の回路以外の他の回路のアースラインを基
板アースに接続するように構成したので、上記複数の回
路と基板間の寄生容量・抵抗を一致させることができ、
同一特性を得ようとする上記複数の回路の特性を一致さ
せることができる。
As described above, according to the present invention, the ground lines of a plurality of circuits whose characteristics are to be matched are floated from the board ground, and the ground lines of other circuits other than the plurality of circuits are connected to the board ground. With this configuration, it is possible to match the parasitic capacitance and resistance between the multiple circuits and the board,
It is possible to match the characteristics of the plurality of circuits that are trying to obtain the same characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体集積回路を示
す平面図、第2図及び第3図はこの発明の他の2種の実
施例による半導体集積回路の平面図、第4図は従来の半
導体集積回路を示す平面図、第5図は従来の半導体集積
回路の縦断面図である。 1は半導体集積回路、A、Bは同一特性が要求される回
路、Cは他の回路、20はアース点、29は半導体基板
。 なお5図中、同一符号は同一、又は相当部分を示す。 E:回y湧内の8誌 H:口玲睨90巧 20ニア−叉点 A:回路 B1回刷ト C:イセの回ソト
FIG. 1 is a plan view showing a semiconductor integrated circuit according to an embodiment of the present invention, FIGS. 2 and 3 are plan views of semiconductor integrated circuits according to two other embodiments of the invention, and FIG. 4 is a plan view showing a conventional semiconductor integrated circuit. FIG. 5 is a plan view showing a conventional semiconductor integrated circuit, and FIG. 5 is a vertical cross-sectional view of a conventional semiconductor integrated circuit. 1 is a semiconductor integrated circuit, A and B are circuits that require the same characteristics, C is another circuit, 20 is a ground point, and 29 is a semiconductor substrate. Note that in Figure 5, the same reference numerals indicate the same or equivalent parts. E: 8th magazine in Yuuchi H: Rei Kuchi 90 Takumi 20 near intersection A: Circuit B 1st printing C: Ise's episode Soto

Claims (1)

【特許請求の範囲】[Claims] 同一特性が要求される複数の回路と、前記複数の回路以
外の他の回路とが同一基板上に設けられている半導体集
積回路において、前記複数の回路はそのアースラインが
基板アースから浮かされ、前記他の回路はそのアースラ
インが前記基板アースに接続されていることを特徴とす
る半導体集積回路。
In a semiconductor integrated circuit in which a plurality of circuits that require the same characteristics and other circuits other than the plurality of circuits are provided on the same substrate, the plurality of circuits have their ground lines floating from the substrate ground, and A semiconductor integrated circuit characterized in that the ground line of the other circuit is connected to the substrate ground.
JP20195388A 1988-08-15 1988-08-15 Semiconductor integrated circuit Pending JPH0251251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20195388A JPH0251251A (en) 1988-08-15 1988-08-15 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20195388A JPH0251251A (en) 1988-08-15 1988-08-15 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0251251A true JPH0251251A (en) 1990-02-21

Family

ID=16449508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20195388A Pending JPH0251251A (en) 1988-08-15 1988-08-15 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0251251A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58157151A (en) * 1982-03-15 1983-09-19 Mitsubishi Electric Corp Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58157151A (en) * 1982-03-15 1983-09-19 Mitsubishi Electric Corp Semiconductor integrated circuit device

Similar Documents

Publication Publication Date Title
JPS58119670A (en) semiconductor equipment
JPS5984542A (en) High-frequency semiconductor integrated circuit
JPS63147357A (en) Electrostatic discharge protection circuit
EP0661744A1 (en) Semiconductor integrated circuit device
JPH0526368B2 (en)
US4968901A (en) Integrated circuit high frequency input attenuator circuit
EP0754352B1 (en) ARRAY ARCHITECTURE WITH ENHANCED ROUTING FOR LINEAR ASICs
EP0348017A2 (en) Semiconductor integrated-circuit apparatus
JPH0251251A (en) Semiconductor integrated circuit
JP2752832B2 (en) Semiconductor integrated circuit device
JPH0547943A (en) Semiconductor integrated device
JP2838662B2 (en) Automotive semiconductor integrated circuits
US3544860A (en) Integrated power output circuit
EP0136888B1 (en) Large scale integration circuitry
JPH0521714A (en) Overvoltage protection circuit
EP0586163B1 (en) Method and configuration for reducing electrical noise in integrated circuit devices
JPH0453104B2 (en)
US5045915A (en) Semiconductor integrated circuit device
EP0473144A2 (en) Semiconductor integrated circuit comprising interconnections
JPH0153512B2 (en)
JP2811740B2 (en) Integrated circuit
JPH0453103B2 (en)
JPH051239U (en) Semiconductor integrated circuit
KR870003570A (en) Semiconductor devices
JPH03120848A (en) Semiconductor integrated circuit