JPH0249229U

JPH0249229U -

Info

Publication number: JPH0249229U
Application number: JP12724188U
Authority: JP
Priority date: 1988-09-30
Filing date: 1988-09-30
Publication date: 1990-04-05

Description

[Brief explanation of drawings]

第１図乃至第３図はこの考案に係るＰＬＬ回路
の実施例を示し、第１図はブロツク図、第２図は
動作点を示す位相比較回路の特性図、第３図は他
の実施例を示すブロツク図である。第４図乃至第
９図は従来の実施例を示し、第４図は従来のブロ
ツク図、第５図は位相比較回路の理想的な特性を
示す特性図、第６図及び第７図は不感帯を有する
従来の位相比較回路の一般的な特性図、第８図は
他の実施例を示す従来のブロツク図、第９図は第
４図及び第８図に示す位相比較回路の動作点を示
す特性図である。主な符号の説明、１：電圧制御発振回路、２：
プログラマブル分周回路、３：位相比較回路、４
：水晶発振回路、５：アクテイブローパスフイル
タ回路、７：電源、９：動作点調整回路、Ａ：不
感帯、Ｂ１，Ｂ２：動作点。 1 to 3 show an embodiment of the PLL circuit according to this invention, FIG. 1 is a block diagram, FIG. 2 is a characteristic diagram of the phase comparator circuit showing operating points, and FIG. 3 is another embodiment. FIG. 4 to 9 show conventional embodiments, FIG. 4 is a conventional block diagram, FIG. 5 is a characteristic diagram showing ideal characteristics of the phase comparison circuit, and FIGS. 6 and 7 are dead zones. FIG. 8 is a conventional block diagram showing another embodiment, and FIG. 9 shows operating points of the phase comparison circuit shown in FIGS. 4 and 8. It is a characteristic diagram. Explanation of main symbols, 1: Voltage controlled oscillation circuit, 2:
Programmable frequency divider circuit, 3: Phase comparison circuit, 4
: Crystal oscillation circuit, 5: Active low-pass filter circuit, 7: Power supply, 9: Operating point adjustment circuit, A: Dead zone, B1, B2: Operating point.

Claims

[Claims for Utility Model Registration] In a PLL circuit consisting of a voltage controlled oscillation circuit, a programmable frequency divider circuit, a phase comparison circuit, a crystal oscillation circuit, and an active low-pass filter circuit, an operation for adjusting the operating point of the phase comparison circuit. A PLL circuit characterized by having a point adjustment circuit.