JPH0241906B2 - - Google Patents
Info
- Publication number
- JPH0241906B2 JPH0241906B2 JP58207720A JP20772083A JPH0241906B2 JP H0241906 B2 JPH0241906 B2 JP H0241906B2 JP 58207720 A JP58207720 A JP 58207720A JP 20772083 A JP20772083 A JP 20772083A JP H0241906 B2 JPH0241906 B2 JP H0241906B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- chip
- composite material
- material film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置に関し、特に素子形成さ
れた半導体チツプを、そのチツプ表面が下向き、
いわゆるフエイスダウンになるようにして、セラ
ミツク基板などにボンデイングさせた半導体装置
に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and in particular, a semiconductor chip having elements formed thereon, with the surface of the chip facing downward.
This relates to a semiconductor device bonded to a ceramic substrate or the like in a so-called face-down manner.
従来例によるこの種の半導体装置の概要構成を
第１図に示す。すなわち、この第１図構成におい
て、符号１は素子形成された半導体チツプ、２は
この半導体チツプ１の電極上に形成された金属バ
ンプ電極、３はこの半導体チツプ１のボンデイン
グ基板としてのセラミツク基板、４はこのセラミ
ツク基板３上に形成された金属配線、５はその保
護絶縁膜である。
FIG. 1 shows a schematic configuration of a conventional semiconductor device of this type. That is, in the configuration shown in FIG. 1, reference numeral 1 indicates a semiconductor chip on which elements are formed, 2 indicates a metal bump electrode formed on the electrode of this semiconductor chip 1, 3 indicates a ceramic substrate as a bonding substrate for this semiconductor chip 1, 4 is a metal wiring formed on this ceramic substrate 3, and 5 is a protective insulating film thereof.
そしてこの従来例装置の場合には、まず半導体
ウエハ製造工程において、半導体素子部の電極上
に金、銀、半田などの金属バンプ電極２を形成さ
せ、ついでこのウエハから半導体チツプ１を切り
出したのち、この半導体チツプ１をあらかじめ金
属配線４の施されたセラミツク基板３に、そのチ
ツプ表面が下向きになるようにして位置合わせ
し、熱着あるいは熱圧着により全ての電極を同時
にボンデイングさせる。すなわち、このように半
導体装置にいわゆるフリツプチツプ方式のボンデ
イングを採用することによつて、素子の高機能化
に伴なうピン数の増加に対処できて、マルチチツ
プモジユールなどの高密度実装が可能になるので
ある。 In the case of this conventional device, first, in the semiconductor wafer manufacturing process, metal bump electrodes 2 made of gold, silver, solder, etc. are formed on the electrodes of the semiconductor element part, and then semiconductor chips 1 are cut out from this wafer. This semiconductor chip 1 is positioned on a ceramic substrate 3 on which metal wiring 4 has been previously provided, with the chip surface facing downward, and all electrodes are bonded simultaneously by heat bonding or thermocompression bonding. In other words, by adopting the so-called flip-chip bonding method for semiconductor devices, it is possible to cope with the increase in the number of pins that accompany the increasing functionality of devices, making it possible to implement high-density packaging such as multi-chip modules. It becomes.
しかしながらこのフリツプチツプボンデイング
による従来例装置では、その構成上から次のよう
な欠点を生ずるものであつた。 However, the conventional device using flip-chip bonding has the following drawbacks due to its construction.
(a) 熱ストレスによる半導体チツプ１およびセラ
ミツク基板３の撓みに対して、これらの相互を
バンプ電極２のみにより支持させているため
に、このバンプ電極２と半導体チツプ１および
セラミツク基板３との間に加えられる応力と
か、バンプ材料の金属疲労による配線部分の断
線を生じ易く、しかもこれは半導体チツプ保護
のための樹脂モールドをなすときの熱ストレス
についても全く同様である。(a) With respect to the bending of the semiconductor chip 1 and the ceramic substrate 3 due to thermal stress, since these are mutually supported only by the bump electrodes 2, the gap between the bump electrodes 2 and the semiconductor chip 1 and the ceramic substrate 3 is The stress applied to the bump material or the metal fatigue of the bump material tends to cause disconnection of the wiring portion, and the same is true for thermal stress when forming a resin mold to protect the semiconductor chip.
(b) 熱ストレスの影響を小さくするために、金属
バンプ電極２をチツプ中心に集めるとか（求心
バンプ）、同中心に均等に配置するなどの対策
が必要となり、これが半導体素子設計の際の制
約条件となつて、その適用範囲が限られてしま
うことになる。(b) In order to reduce the effects of thermal stress, it is necessary to take measures such as gathering the metal bump electrodes 2 at the center of the chip (centripetal bump) or arranging them evenly in the same center, which poses constraints when designing semiconductor devices. As a result, its scope of application will be limited.
(c) 熱ストレスの影響を小さくするためには、半
導体チツプ１とセラミツク基板３との間隔を数
十μｍ程度に維持することが要求されるが、熱
着あるいは熱圧着によるボンデイング方法では
この間隔を所定値内に設定するのが困難であ
る。(c) In order to reduce the effects of thermal stress, it is necessary to maintain the distance between the semiconductor chip 1 and the ceramic substrate 3 at approximately several tens of μm, but bonding methods using thermal bonding or thermocompression bonding do not allow this distance. is difficult to set within a predetermined value.
この発明は従来のこのような欠点に鑑み、金属
線材と絶縁性樹脂とからなる一方向導電性の複合
材料フイルムを介し、素子形成された半導体チツ
プとボンデイング基板のチツプ側金属層とボンデ
イング基板の基板側金属層とを電気的に結合させ
て、フリツプチツプにより形成される半導体装置
の熱ストレス耐性を向上させ、併せてその適用範
囲を拡大させるようにしたものである。
In view of the above-mentioned drawbacks of the conventional technology, the present invention has been developed to connect a semiconductor chip on which an element is formed, a chip-side metal layer of a bonding substrate, and a bonding substrate via a unidirectionally conductive composite material film made of a metal wire and an insulating resin. The semiconductor device is electrically coupled to a metal layer on the substrate side to improve the thermal stress resistance of a semiconductor device formed by a flip chip, and to expand its range of application.
以下この発明に係る半導体装置の実施例につ
き、第２図ないし第５図を参照して詳細に説明す
る。
Embodiments of the semiconductor device according to the present invention will be described in detail below with reference to FIGS. 2 to 5.
これらの第２図ないし第５図実施例装置におい
て前記第１図従来例装置と同一符号は一または相
当部分を示している。 In the apparatus of the embodiment shown in FIGS. 2 to 5, the same reference numerals as in the conventional apparatus shown in FIG. 1 indicate one or a corresponding part.
第２図は第１実施例による半導体装置を前記第
１図従来例装置に対応して表しており、符号６は
前記金属バンプ電極２に換えて半導体チツプ１の
電極上に形成された金、半田などのチツプ側金属
層、７は金属線材８を絶縁性樹脂９内の厚さ方向
に相互に絶縁させて高密度に埋め込んで形成させ
た一方向導電性の複合材料フイルム、１０は前記
セラミツク基板３の金属配線４上に形成された
金、半田などの基板側金属層である。そしてこの
第１実施例による半導体装置の場合には、この第
２図構成からも明らかなように、一方向導電性の
複合材料フイルム７を介して、半導体チツプ１と
セラミツク基板３とを熱着あるいは熱圧着により
ボンデイング結合させるようにしたものである。 FIG. 2 shows a semiconductor device according to a first embodiment corresponding to the conventional device shown in FIG. A metal layer on the chip side such as solder, 7 is a unidirectional conductive composite material film formed by embedding metal wires 8 in an insulating resin 9 with mutual insulation in the thickness direction at a high density, and 10 is the ceramic film. This is a substrate-side metal layer of gold, solder, etc. formed on the metal wiring 4 of the substrate 3. In the case of the semiconductor device according to the first embodiment, as is clear from the configuration in FIG. Alternatively, the bonding may be performed by thermocompression bonding.
こゝで前記一方向導電性の複合材料フイルム７
としては、第３図に示したように、例えば絶縁性
樹脂９の内部にあつて、直径10〜50μｍ程度、長
さ50〜200μｍ程度の銅、金、銀などの金属線材
８を、10〜50μｍ程度の高密度間隔で厚さ方向に
埋め込んで形成させたものを用いる。従つてこの
複合材料フイルム７は、電気的に厚さ方向のみの
一方向導電性（電気的異方性）を有し、また機械
的に厚さ方向に剛性、横方向に柔性（機械的異方
性）を有することになる。すなわち、このような
複合材料フイルム７のもつ性質を利用して、一方
では電気的異方性により、半導体チツプ１上の複
数の電極間を相互に絶縁させた状態でセラミツク
基板３と結合させ、他方では機械的異方性によ
り、半導体チツプ１とセラミツク基板３との熱膨
張係数の差によつて結合部に生ずる応力を吸収、
緩和させるのである。 Here, the unidirectional conductive composite material film 7
As shown in FIG. 3, for example, inside an insulating resin 9, a metal wire 8 made of copper, gold, silver, etc., with a diameter of about 10 to 50 μm and a length of about 50 to 200 μm, is placed between 10 to 50 μm. It is formed by embedding it in the thickness direction at high density intervals of about 50 μm. Therefore, this composite material film 7 electrically has unidirectional conductivity (electrical anisotropy) only in the thickness direction, and mechanically has rigidity in the thickness direction and flexibility (mechanical anisotropy) in the lateral direction. It will have a certain orientation (orientation). That is, by utilizing the properties of such a composite material film 7, on the one hand, the plurality of electrodes on the semiconductor chip 1 are bonded to the ceramic substrate 3 in a state in which they are insulated from each other due to electrical anisotropy; On the other hand, mechanical anisotropy absorbs the stress generated in the joint due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the ceramic substrate 3.
It eases it.
次に前記第１実施例装置でのフリツプチツプ方
式のボンデイング手順を第４図ａ，ｂ，ｃについ
て述べる。 Next, the flip-chip bonding procedure in the first embodiment will be described with reference to FIGS. 4a, b, and c.
まず同図ａに示すように、セラミツク基板３側
のボンデイング部分には、あらかじめ金、半田な
どの基板側金属層１０を５〜20μｍ程度形成して
おく。ついで同図ｂのように、複合材料フイルム
７をこのセラミツク基板３のボンデイング部分に
熱着あるいは熱圧着により結合させ、実質的にセ
ラミツク基板３上の金属配線４と複合材料フイル
ム７の金属線材８とを電気的に接続させるが、こ
のときセラミツク基板３に対して複合材料フイル
ム７を特別に位置合わせする作業は一切不用であ
つて、単に基板側金属層１０を複合材料フイルム
７で覆うように配置させさえすればよいことにな
る。さらに半導体チツプ１の電極上にもあらかじ
め金、半田などのチツプ側金属層６を５〜20μｍ
程度形成しておき、同図ｃのように、この半導体
チツプ１を表面が下向きになるようにして複合材
料フイルム７上に位置合わせしてから、同様に熱
着あるいは熱圧着により結合させるのである。 First, as shown in FIG. 1A, a substrate-side metal layer 10 of gold, solder, or the like is formed in advance to a thickness of about 5 to 20 μm on the bonding portion of the ceramic substrate 3 side. Then, as shown in FIG. 2B, the composite material film 7 is bonded to the bonding portion of the ceramic substrate 3 by heat bonding or thermocompression bonding, thereby substantially bonding the metal wiring 4 on the ceramic substrate 3 and the metal wire 8 of the composite material film 7. However, at this time, there is no need to perform any special positioning of the composite material film 7 with respect to the ceramic substrate 3; simply cover the substrate side metal layer 10 with the composite material film 7. All you have to do is place it. Furthermore, on the electrodes of the semiconductor chip 1, a chip-side metal layer 6 of gold, solder, etc. is applied in advance to a thickness of 5 to 20 μm.
After the semiconductor chip 1 is aligned with the composite material film 7 with its surface facing downward, as shown in FIG. .
すなわち、このようにして第１実施例装置にお
いては、半導体チツプ１とセラミツク基板３との
熱膨張係数の差に起因して、熱ストレス印加時に
結合部に加えられる応力を複合材料フイルム７に
より充分に吸収、緩和させることができ、これに
よつてフリツプチツプにより形成される半導体装
置の熱ストレス耐性を向上させ得るである。 That is, in this way, in the device of the first embodiment, the composite material film 7 sufficiently absorbs the stress applied to the bonding portion when thermal stress is applied due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the ceramic substrate 3. This can improve the thermal stress resistance of semiconductor devices formed by flip chips.
なお、前記第１実施例においては、半導体チツ
プ１の全面に複合材料フイルム７を配置させた場
合について説明したが、第５図に示す第２実施例
のように、半導体チツプの電極部分にのみ配置さ
せるようにしてもよいことは勿論である。そして
またボンデイング手順としても、前記とは反対に
半導体チツプ側に複合材料フイルムを結合したの
ち、これをボンデイング基板上に結合させてもよ
い。 In the first embodiment, the composite material film 7 is arranged on the entire surface of the semiconductor chip 1, but as in the second embodiment shown in FIG. Of course, it is also possible to arrange them. Also, as a bonding procedure, contrary to the above, the composite material film may be bonded to the semiconductor chip side and then bonded onto the bonding substrate.
以上詳述したようにこの発明によれば、フリツ
プチツプ方式のボンデイングを採用した半導体装
置において、金属線材を絶縁性樹脂内の厚さ方向
に相互に絶縁させて高密度に埋め込んだ一方向導
電性の複合材料フイルムを用い、この一方向導電
性の複合材料フイルムを介し、素子形成された半
導体チツプのチツプ側金属層とボンデイング基板
の基板側金属層とを電気的に結合させる構成とし
たので、熱着あるいは熱圧着によるボンデイング
に際して、半導体チツプとボンデイング基板との
間に加えられる応力をこの複合材料フイルムによ
り吸収、緩和し得て装置の熱ストレス耐性を向上
でき、これによつて半導体チツプおよびボンデイ
ング基板それぞれの配線部の断線を防止できると
共に、素子設計の制約条件も緩和されて適用範囲
が拡大され、また半導体チツプとボンデイング基
板との間隔を正確に所定値内に維持できて装置の
特性向上に役立つなどの特長を有するものであ
る。
As detailed above, according to the present invention, in a semiconductor device employing flip-chip bonding, a unidirectionally conductive metal wire in which metal wires are mutually insulated in the thickness direction and embedded at high density in an insulating resin is used. By using a composite material film, the metal layer on the chip side of the semiconductor chip on which the element is formed and the metal layer on the substrate side of the bonding substrate are electrically connected via this unidirectionally conductive composite material film, so that heat can be avoided. During bonding by bonding or thermocompression bonding, the stress applied between the semiconductor chip and the bonding substrate can be absorbed and alleviated by this composite material film, improving the thermal stress resistance of the device. In addition to preventing disconnections in each wiring section, the constraints on element design are relaxed, expanding the scope of application, and the distance between the semiconductor chip and the bonding substrate can be accurately maintained within a predetermined value, improving the characteristics of the device. It has features such as being useful.
また、半導体チツプおよびボンデイング基板は
それぞれ金属層を予め形成しておき、この金属層
を介して複合材料フイルムと接触するため、半導
体チツプおよびボンデイング基板に直接熱ストレ
スが加わるのを防止することができ、半導体装置
の信頼性を高めることができるという効果があ
る。 In addition, since the semiconductor chip and the bonding substrate each have a metal layer formed in advance and come into contact with the composite film through this metal layer, it is possible to prevent direct thermal stress from being applied to the semiconductor chip and the bonding substrate. This has the effect of increasing the reliability of the semiconductor device.
第１図は従来例のフリツプチツプ方式による半
導体装置の概要を示す断面構成図、第２図はこの
発明の第１実施例での同上半導体装置の概要を示
す断面構成図、第３図は同上実施例装置に用いる
一方向導電性の複合材料フイルムの一例を示す部
分斜視図、第４図ａ，ｂ，ｃは同上実施例装置の
組立て手順を順次に示す断面図、第５図はこの発
明の第２実施例での同上半導体装置の概要を示す
断面構成図である。
１……半導体チツプ、３……セラミツク基板
（ボンデイング基板）、４……金属配線、６……チ
ツプ側金属層、７……一方向導電性の複合材料フ
イルム、８……金属線材、９……絶縁性樹脂、１
０……基板側金属層。
FIG. 1 is a cross-sectional configuration diagram showing an overview of a conventional flip-chip type semiconductor device, FIG. 2 is a cross-sectional configuration diagram showing an overview of the same semiconductor device according to a first embodiment of the present invention, and FIG. A partial perspective view showing an example of a unidirectionally conductive composite material film used in the example device; Figures 4a, b, and c are cross-sectional views sequentially showing the assembly procedure of the example device; FIG. 7 is a cross-sectional configuration diagram showing an outline of the semiconductor device according to the second embodiment. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 3... Ceramic substrate (bonding board), 4... Metal wiring, 6... Chip side metal layer, 7... Unidirectional conductive composite material film, 8... Metal wire, 9... ...Insulating resin, 1
0...Substrate side metal layer.
Claims (1)
絶縁させて高密度に埋め込んだ一方向導電性の複
合材料フイルムを用い、この一方向導電性の複合
材料フイルムを介して、素子形成された半導体チ
ツプの電極上に形成されたチツプ側金属層とボン
デイング基板の金属配線上に形成された基板側金
属層とを電気的に結合させたことを特徴とする半
導体装置。1 Using a unidirectionally conductive composite material film in which metal wires are mutually insulated and embedded in an insulating resin in the thickness direction at a high density, an element is formed through this unidirectionally conductive composite material film. A semiconductor device characterized in that a chip-side metal layer formed on an electrode of a semiconductor chip and a substrate-side metal layer formed on a metal wiring of a bonding substrate are electrically coupled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58207720A JPS60100441A (en) | 1983-11-05 | 1983-11-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58207720A JPS60100441A (en) | 1983-11-05 | 1983-11-05 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60100441A JPS60100441A (en) | 1985-06-04 |
| JPH0241906B2 true JPH0241906B2 (en) | 1990-09-19 |
Family
ID=16544430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58207720A Granted JPS60100441A (en) | 1983-11-05 | 1983-11-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60100441A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62101042A (en) * | 1985-10-28 | 1987-05-11 | Minolta Camera Co Ltd | Loading structure to substrate of ic chip |
| JP2500462B2 (en) * | 1993-07-22 | 1996-05-29 | 日本電気株式会社 | Inspection connector and manufacturing method thereof |
| WO2019022902A1 (en) | 2017-07-24 | 2019-01-31 | Cerebras Systems Inc. | Apparatus and method for multi-die interconnection |
| US10468369B2 (en) * | 2017-07-24 | 2019-11-05 | Cerebras Systems Inc. | Apparatus and method for securing substrates with varying coefficients of thermal expansion |
| WO2019040273A1 (en) | 2017-08-24 | 2019-02-28 | Cerebras Systems Inc. | Apparatus and method for securing components of an integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5693337A (en) * | 1979-12-26 | 1981-07-28 | Fujitsu Ltd | Semiconductor device |
-
1983
- 1983-11-05 JP JP58207720A patent/JPS60100441A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60100441A (en) | 1985-06-04 |
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