JPH0239095B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a method for manufacturing a MOS type semiconductor device,
In particular, this invention relates to improvements in the method of introducing impurities that form sources and drains.

(Technical background of the invention and its problems) As shown in FIG. 1, a conventional MOS type semiconductor device forms a gate electrode 2 on the surface of a semiconductor substrate 1 via a gate oxide film, and then diffuses impurities. A method of forming the source 3 and drain 4 is generally used.

In this method, when the impurity is diffused, the diffusion also progresses in the lateral direction, and the diffusion layers that will become the source 3 and drain 4 invade below the gate electrode 2, and the overlapping region 5
is formed. The formation of such an overlapping region 5 increases the coupling capacitance, slowing down the rise of the gate potential, and causing a problem of slowing down the operating speed of the circuit.

In order to improve this problem, a method as shown in FIG. 2 has been developed.

In this method, first, as shown in FIG. 2A, polycrystalline silicon is provided on the surface of a semiconductor substrate 1 via a gate oxide film 6 to form a gate electrode 2, and then this surface is oxidized to form an oxide film 7. form, and then cover the entire surface
A polycrystalline silicon film 8 is deposited by CVD method.

Next, when the polycrystalline silicon film 8 on the surface is etched by an anisotropic etching method, the polycrystalline silicon film 8 located on both sides of the gate electrode 2 remains without being etched, as shown in FIG. 2B. In this state, using the gate electrode 2 and the polycrystalline silicon films 8 remaining on both sides thereof as masks, impurity ions are implanted into the semiconductor substrate 1 by a known ion implantation method to form an ion implantation layer 9. Thereafter, the ion implantation layer 9 is diffused by heat treatment to form a source 3 and a drain 4 as shown in FIG. 2C.

In the above conventional method, the polycrystalline silicon 8, 8 is provided on both sides of the gate electrode 2 in an amount equal to the thickness of the polycrystalline silicon, that is, the width of the ion implantation layer 9 in the lateral direction. There is no overlapping region with the source 3 and drain 4, and high speed can be achieved.

However, in the above method, in the step of anisotropically etching the polycrystalline silicon film 8, etching progresses slightly in the lateral direction.
The film thickness could not be sufficiently controlled, resulting in variations in properties and a reduction in yield.

(Object of the Invention) The present invention has been made in view of the above points, and it prevents the lateral etching of the film left as a mask on both sides of the gate electrode and forms a mask with good controllability, thereby forming a mask between the gate electrode and the gate electrode. ,sauce·
MOS that has no coupling capacitance due to overlap with the drain and can produce high-speed products with high yield.
The present invention provides a method for manufacturing a type semiconductor device.

(Summary of the Invention) That is, the method of the present invention includes a step of forming a gate electrode on the surface of a semiconductor substrate, a step of depositing a first film on the entire surface, and a step of depositing a first film on the entire surface of the semiconductor substrate. a step of forming a second coating having a different temperature; a step of anisotropically etching the second coating so that the second coating remains only on the side surface of the stepped portion of the first coating; a step of anisotropically etching the film to leave first and second films on both sides of the gate electrode; and introducing impurities into the semiconductor substrate using the gate electrode and the film remaining on both sides as a mask. The method is characterized by comprising a step of forming a source/drain.

The method of the present invention will be explained in detail below.

As a MOS type semiconductor device to which the method of the present invention is applied, it is suitable for a P-channel MOS semiconductor in which the source and drain are formed using boron with a large diffusion coefficient, and is effective for manufacturing a P-channel element of a CMOS semiconductor device. It is. Also FAMOS
In addition to floating gate MOS type semiconductor devices such as SAMOS, it is also effective in manufacturing high voltage MOS type semiconductor devices.

In the present invention, the first film includes, for example, a polycrystalline silicon film, silicon nitride film, molybdenum silicide, or silicon oxide film, which is deposited over the entire surface with a film thickness corresponding to the lateral diffusion of impurities. let

As the second film used in the present invention, for example, a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film is used. These need to be a combination of different types that have different etching properties than the first coating, that is, a combination that has a slow etching rate during anisotropic etching of each of the first and second coatings. When a polycrystalline silicon film is used, a silicon oxide film or a silicon nitride film is used as the second film, and these are formed thinner than the first film by a deposition method, an oxidation method, a nitridation method, or the like.

Furthermore, in the present invention, for example, polycrystalline silicon, metal silicide, metal, etc. may be used as the gate electrode, and the surface thereof may be covered with an insulating film such as a silicon oxide film and used as a stopper during etching of the first film. good.

(Embodiments of the Invention) Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 3A to 3D show one embodiment of the present invention step by step. First, as shown in FIG. 3A, a polycrystalline silicon film is provided on the surface of a semiconductor substrate 1 such as a silicon substrate with a gate oxide film 6 interposed therebetween.
This is patterned to form the gate electrode 2. Next, the entire surface is thermally oxidized to form a silicon oxide film 10 on the surface of the gate electrode 2. After this, completely
Polycrystalline silicon film 8 is deposited to a thickness of 3000 Å using the CVD method.
The entire surface of the silicon oxide film 11 is thermally oxidized to form a silicon oxide film 11 with a thickness of 300 Å.

Next, the silicon oxide film 1 on the surface is etched by anisotropic etching such as reactive ion etching.
When etching 1 is selectively etched, the silicon oxide films 11, 11 located on both sides of gate electrode 2, which are convex portions as shown in FIG. 3B, remain without being etched. In this case, the remaining silicon oxide film 11 will be side-etched to some extent, but it is sufficient to leave it in a thin layer.

After this, anisotropic etching is again performed to selectively etch the exposed polycrystalline silicon film 8, and as shown in FIG. 3C, the exposed portion is removed and the convex gate Polycrystalline silicon films 8 located on both sides of electrode 2 remain. In this case, since the surfaces of the polycrystalline silicon films 8, 8 located on both sides of the gate electrode 2 are covered with the silicon oxide films 11, 11 left in the previous step, side etching is not possible even during anisotropic etching. The polycrystalline silicon films 8, 8 can remain at the same thickness as they were deposited without being damaged.

Next, using the gate electrode 2 and polycrystalline silicon films 8, 8 provided on both sides thereof and whose surfaces are covered with silicon oxide films 11, 11 as masks, impurities such as boron are added to the semiconductor substrate 1 by a known method. An ion implantation layer 9 is formed by ion implantation.

Thereafter, the ion implantation layer 9 is diffused by heat treatment using a known method to form a source 3 and a drain 4 as shown in FIG. 3D.

In the above method, even if lateral diffusion occurs due to diffusion of the ion-implanted layer 9, the polycrystalline silicon films 8, 8, which serve as a mask for the overlapping region with a desired width, can remain without undergoing side etching. With good reproducibility, gate electrode 2, source 3,
Overlapping with the drain 4 can be prevented.

Next, an embodiment in which the present invention is applied to the formation of a P channel element of a CMOS semiconductor device will be described.

In P-channel elements of CMOS semiconductor devices, boron is usually used to form the source and drain diffusion layers, but since boron has a large diffusion coefficient, the coupling capacitance is larger than that of N-channel elements, and the gate electrode The rise time will be slower.

Therefore, in the method of the present invention, after depositing the polycrystalline silicon film 8 as the first film, and forming the silicon oxide film 11 thereon as the second film, these are each anisotropically etched as described above. At this time, the N-channel device region 12 is covered with a mask using photolithography technology, and only the P-channel device region 13 is selectively etched to form a polygonal layer covered with the silicon oxide film 11 only on both sides of the gate electrode 2. The crystalline silicon film 8 is left. After this, boron is ion-implanted and diffused using a known method.
A source 3 and a drain 4 are formed to form a CMOS semiconductor device as shown in FIG.

In this case, in the N-channel device region 12, the gate electrode 2, the source 3, and the drain 4 overlap only slightly, and in the P-channel device region 13 formed in the conductivity region 14 opposite to the conductivity type of the semiconductor substrate 1, boron is diffused. Gate electrode 2 although it is easy to
It is possible to prevent the source 3 and the drain 4 from overlapping with each other.

Next, an embodiment will be described in which the method of the present invention is applied to manufacturing a MOS type semiconductor device having a floating gate structure such as FAMOS or SAMOS.

First gate electrode 2 having a floating structure
After forming the gate electrode a and the second gate electrode 2b, a polycrystalline silicon film 8 and a silicon oxide film 11 are formed on the entire surface in the same manner as in the above embodiment. Next, these are sequentially anisotropically etched to form the first and second electrodes 2.
The polycrystalline silicon film 8 covered with the silicon oxide film 11 is left on both sides of a and 2b. Next, using these as a mask, boron ions are implanted and further diffused to form a source 3 and a drain 4, thereby obtaining a MOS type semiconductor device as shown in FIG.

As a result, the potential of the first gate electrode 2a is no longer pulled by the potential of the drain 4 and fluctuated due to capacitive coupling between the first gate electrode 2a and the drain 4, thereby preventing leakage during writing in non-selected cells. can do.

Furthermore, the method of the present invention forms a deep junction between the source 3 and drain 4 to avoid electric field concentration and is suitable for high breakdown voltage applications.
If applied to the manufacture of MOS semiconductor devices, it can be used for high breakdown voltages where it is easy to form overlapping regions by forming them deeply.
Even in the case of MOS, overlapping can be reliably prevented.

(Effects of the Invention) As explained above, according to the method of manufacturing a MOS type semiconductor device according to the present invention, the gate electrode and the source
By preventing overlap with the drain, high-speed products with no coupling capacitance can be manufactured with high yield.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a conventional MOS type semiconductor device, FIGS. 2A to C are cross-sectional views showing a method for manufacturing a MOS type semiconductor device by a conventional method, step by step, and FIGS. 3A to D are 4 is a cross-sectional view showing a method for manufacturing a MOS type semiconductor device according to an embodiment of the present invention according to the sequential steps. FIG. 4 is a sectional view of a CMOS semiconductor device according to another embodiment of the present invention. FIG. FIG. 4 is a cross-sectional view of a MOS type semiconductor device having a floating gate structure according to another embodiment having a different structure. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Gate electrode, 3... Source, 4... Drain, 5... Overlapping region, 6... Gate oxide film, 7... Oxide film, 8... Polycrystalline silicon film, 9
...Ion implantation layer, 10,11...Silicon oxide film,
12...N channel element region, 13...P channel element region.

Claims (1)

[Claims] 1. A step of forming a gate electrode on the surface of a semiconductor substrate, a step of depositing a first film on the entire surface, and a step of depositing a second film on the entire surface of the first film, which has a different etching property. a step of anisotropically etching this second film so that the second film remains only on the side surface of the stepped portion of the first film;
a step of anisotropically etching the first coating to leave the first and second coatings on both sides of the gate electrode; 1. A method for manufacturing a MOS semiconductor device, comprising the step of introducing impurities into a substrate to form a source and drain. 2. Claim 1, characterized in that the second coating is formed thinner than the first coating.
A method for manufacturing a MOS type semiconductor device. 3. The method according to claim 1, wherein the surface of the gate electrode is covered with an insulating film.
A method for manufacturing a MOS type semiconductor device. 4. Manufacturing a MOS semiconductor device according to claim 1 or 2, characterized in that a polycrystalline silicon film, a silicon nitride film, a molybdenum silicide film, or a silicon oxide film is used as the first film. Method. 5. A method of manufacturing a MOS type semiconductor device according to claim 1 or 2, characterized in that a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film is used as the second film.