JPH0232648B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an information processing device that automatically changes the structure of hardware or firmware depending on the nature of the software used.

Prior Art and Problems Conventionally, computers have been designed according to a predetermined hardware configuration or logic, apart from functional expansion. Therefore, when various programs are run, the performance of the computer changes greatly depending on the content of the programs. For example, there is a difference in performance between an office processing program that frequently accesses external memory and a science and technology program that uses many internal registers, depending on the structure of the computer used, such as whether more data registers or instruction registers are reserved. appears large.

For this reason, even if you try to design any program to improve its performance on a general-purpose computer, it is extremely difficult for the reasons mentioned above.
Conventionally, countermeasures have been considered, such as (1) system settings using configuration control, and (2) changing the internal logic of the hardware using OPSR (Operation Status Register), but the former is determined at the time of system installation. In the latter case, the operator mainly changes the OPSR, which places a heavy burden on the operator.
Also, both have no flexibility when the program changes (such as TSS).

Purpose of the Invention In order to solve the above-mentioned problems, the present invention automatically changes the structure (configuration or logic) of hardware or firmware so that the computer itself is suitable for software, that is, a collection of various instructions. It allows you to change it.

Structure of the Invention The present invention provides an information processing device having hardware or firmware, which includes a control unit that determines the nature of software currently being executed, and a control unit that determines the configuration or logic of the hardware or firmware in accordance with the determination result. The control unit records one or more types of commands input or executed within a predetermined period, and from the results, or The present invention is characterized in that the usage status of the hardware is recorded and the above-mentioned judgment is made based on the results. This will be explained in detail below with reference to the drawings.

Embodiments of the Invention In a computer that aims to increase speed, such as a vector processor, multiple instructions and multiple external data processed by the instructions are buffered, and subsequent instructions in the program are changed depending on the state of the computer, etc. It may be executed before the preceding instruction (instruction overtaking). To this end, a plurality of instructions and external data are loaded into an instruction holding unit (iR) and a data holding unit (DR), respectively, and the order and timing of issuing instructions is controlled.

As an example of this, a conventional vector instruction control device (VIu) is shown in FIG. It is assumed that this command control device consists of a command fetching circuit 1 and a command issuing circuit 2, and two pieces of data (first and second) are input for one command. 3 sends instructions and data to external devices such as external memory and auxiliary processors. A buffer 4 in the instruction fetching circuit 1 buffers instructions and data from the external device 3. A flag control circuit 5 manages data. iR ₀ to ₃ are instruction registers,
_AR0-3 are data address registers, _DRF is a first data register, _DRS is _a second data register, and CL is a clock. Also, SEL is a select circuit, 101 is a bus line that transmits instructions and data, 110 is an address line that indicates data to be processed by the iR _O instruction, 111 is a read (READ) address line for data register DR, and 112 is an issued instruction This is an address line that indicates the storage location of data to be processed.

Information is sent from the external device 3 in the order of command, first data, and second data (repetition of this), and is held in the buffer 4. Information is taken out from buffer 4 in the same order, and clocks C _O ,
When CI _DF and CL _DS are turned on in sequence, the instruction is set to the instruction register _iRO , and the two data are set to the data registers _DRF and _DRS, respectively. Furthermore, when the clock _CLO is turned on, the flag control circuit 5 selects one of the addresses (0 to 3 in the illustrated example) of the data register DR whose flag (described later) is turned off. 110 to the address register _ARO . The contents of the address register _ARO are then written (WRiTE) to the data registers _DRF and _DRF , respectively, when the clocks _CLDF and _DLDS are turned on.
It becomes an address (signal line 113). In the instruction generation circuit 2, instruction registers iR1 to iR3
When one of the clocks becomes vacant, one of the clocks CL ₁ to _{CL 3}
is turned on, and the corresponding instruction register and address register are set to register.
Import the contents of iR _O and AR _O. Further, the arithmetic unit (described later) determines the command to be issued based on the context of the instructions, selects one of the registers iR ₁ to iR ₃ in response to the set signal sel, and transmits the command to the arithmetic unit. Simultaneously corresponding address register
One of AR ₁ to _{AR 3} is sent to the flag control circuit 5 through the signal line 112. The flag control circuit 5 transmits the received data to the data register DR through the address signal line 111, and sends the two data 1st and 2nd to the arithmetic unit. The arithmetic unit receives the transmitted command and two pieces of data and processes them.

FIG. 2 is a detailed diagram of the flag control circuit 5.
212 correspond to the signal lines 110 to 112 in FIG. 230 to 233 are the data registers in Figure 1.
This flag indicates whether the data at each address 0 to 3 of the DR is valid or invalid, and uses a set (S)/reset (R) type latch. SET FLAG is a signal that turns on at the same time as the clock _CLO in FIG. 1 turns on, and determines the timing at which flags 230 to 233 are set. START
iNSTRuCTioN is a signal sent from the command transmission circuit 2 shown in FIG.
-233 reset timing is determined. 22
2 is a coder that decodes the address on the signal line 212 and indicates which address the flag belongs to, 221 is a select circuit that indicates a vacant address depending on the state of the flag, and 220 is an encoder that encodes the selected address. . Note that the output ALL BUSY from the select circuit 221 is a signal indicating that data at all addresses are valid and no more data can be taken in. Also, RAR is signal line 2
This register latches the signal on signal line 211 (112 in FIG. 1) and sends it to the data register DR in FIG. 1.

Explain the operation. The select circuit 221 selects the address (the flag is in a reset state) of invalid data (data that has already been sent to the arithmetic unit) (giving priority to the smaller value), encodes it with the encoder 220, and then sends it to the signal line 210 ( It is transmitted to the address register _ARO in FIG. 1 as a signal 110) in FIG. Each address of the data register DR and the flag 230 corresponding to each address
~233 is four in this example, so it is represented by two binary values, 230 is 00, 231 is 11, and 232 is
10,233 has a ratio of 11. Resetting these flags and specifying a free address in the data register DR using these flags are also done using this binary 2 value.
It is done in bits. For example, when only the flag 230 is reset, the signal line 210 becomes 00, the signal line 212 becomes 00, and the flag 230 is reset. When the signal on the signal line 210 is set in the register _ARO by turning on the clock _CLO , the flag (2) of the corresponding address is set at the same time.
30 to 233). Also, when a command is sent from the command sending circuit 2, START
The address of signal line 212 is sent together with iNSTRuCTioN, and the corresponding flag is reset. The address is also latched in the register RAR, and the first address is used as the read address of the signal line 211.
The data is sent to the data register DR shown in the figure, and the data to be processed by the issued command is read out and sent to the arithmetic unit. In addition to the above, all flags 23
When 0 to 233 are set, ALL BUSY
The signal turns on. This signal is the instruction capture circuit 1
It is sent to the control unit that controls the whole, and prevents any further instructions from being taken into register _iRO .

In conventional computers, register iR is fixed for instructions and register DR is fixed for data.
There is no mutual accommodation. However, scientific computers require a large number of data registers,
Office computers require a large number of instruction registers, and a design suitable for one will be inadequate for the other. Therefore, the present invention changes the hardware according to the program.

FIG. 3 shows an embodiment of the present invention, in which, as described above, in a device having a plurality of information holding sections such as the instruction register iR and the data register DR, the balance of their capacities is adjusted according to the nature of the software. It is intended to be changed automatically. In the example in Figure 1, the instruction register
The number of iR _O to iR ₃ and the number of data registers _DRF or _DRS are both 4 (fixed), but there are many actual instructions that do not use external data (for example, instructions that use only internal registers as operands). ), therefore, the usage rate of the data register DR differs depending on the software. Therefore, in this example, an auxiliary information holding section SR is provided so that it can be used both as an iR and as a DR. As is the case throughout all the figures, the same parts in FIG. data register
Both DR _F and DR _S have one stage reduced to three stages,
A data register DR for setting input data on the bus line 301 is selected by an output 327 (designating addresses 0 to 2 of DR) obtained by decoding the signal line 313 by a decoder 324. 300 is a structure change signal which changes registers _SRF and _SRS to instruction and address registers iR _O ′ and AR _O ′, respectively.
(Fig. 4) or as the fourth stage data registers DR _F3 and DR _S3 (Fig. 5). That is, when the signal 300 is 1, the configuration is as shown in FIG. This is automatically achieved by switching selectors 320-323 with signal 300 in FIG. On the other hand, signal 30
When 0 is 0, the configuration is as shown in FIG. This is realized by reversing the states of selectors 320-323 from those shown in FIG. 328 is the output of the decoder 324, and is a signal indicating that data register 3 3, ie, _DRF3 and _DRS3, is selected. In addition, 331 and 332 are clocks C _O ,
This is a switching gate for CL _DF and CL _DS .

In the above example, registers iR O ′, AR _O of the same type as registers iR _O , AR _O of instruction fetch circuit 1 in FIG.
Although AR _O ' has been added, the registers in the instruction issuing circuit 2 may be configured in four stages such as iR ₁ to iR ₄ and AR ₁ to AR ₄ . In either case, the registers _SRF and _SRS that can be used for data are used, so that a portion of the address register AR is unused, as shown by diagonal lines in FIG.

When adopting the configuration shown in FIG. 4, the flag control circuit 5 shown in FIG. 2 must also be changed (because the number of data registers DR is reduced to three). FIG. 6 shows the modified functional part for this purpose. In the same figure, 62
1 and 633 correspond to 221 and 233 in FIG. 2, respectively. 640 is an additional Aogate. 600 is the same structure change signal as 300 in FIG. 3. When this is 1, the output of the blue gate 640 is always 1, and the flags 230 to
232 are all set, which is equivalent to a state in which all three data registers DR are filled with data, and the +ALL BUSY signal becomes 1.

Although the above embodiment has shown an example in which the register configuration of the hardware is automatically changed (depending on the nature of the software will be described later), the hardware to be changed is not limited to this. 7th
The following figure is an example of application to control change of a vector access control device.

In a computer that processes multiple data (vector data) at high speed, it is desirable to use only internal registers (VR) to execute arithmetic instructions, etc., without using the main memory (MEM) as much as possible. This internal register VR, also called a vector register, consists of one or more elements, and each element holds one piece of data. Generally, elements are processed in order starting from element 0, and the results are written to other VRs.
For this purpose, the more VRs the better. Multiple VR
The set of is called a vector register group (VRG), but due to limitations in the capacity of the VRG or the nature of the software, data must be transferred at a certain frequency between the MEM and the VRG.
The memory access control device (VSu) is configured to include, for example, a plurality of access control units (hereinafter referred to as access pipes or simply pipes) to efficiently control the above data transfer.

Figure 7 is a block diagram of the entire information processing device equipped with the function of processing vector data at high speed. 11 is the main memory (MEM), 12 is the memory control unit (MCu), and 13 is one element that processes scalar data. 14 is a channel device (CHP), 15 is an external input/output device (I/
O). Inside the lined frame 16 is a vector data processing unit (Vu: vector unit), which includes a vector register group (VRG) 17, a memory access control unit (VSu) 18, and an instruction control unit (VIu) shown in the previous example. 16 and computing unit (VEu) 20
is included. The VRG 17 is composed of a plurality of vector registers VR as described above, and the arithmetic unit 20 executes various arithmetic instructions using VR as an operand. This arithmetic unit 20 has an ADD for addition.
Adder 20A, MuLTi operator 20B for multiplication,
There is a DiViDE calculator 20C for division. The above-mentioned instruction control device 9 is the memory access control device 1.
8 and the arithmetic unit 20. In the figure, IT indicates instruction transmission, D indicates data, and I indicates the flow of instructions.

FIG. 8 shows an example of the configuration of the VRG 17. This VRG
17 uses, for example, a RAM with an access time of 1τ (Vu clock cycle) or less, and has an interleaved configuration. In other words, elements with the same number in each register VR _O to VR ₂₅₅ that make up VRG are grouped together as a bank, and this bank consists of 8 elements.
One VRG is configured, and the access timings from the plurality of access control units in the VSu are made different (shifted) for each bank. With this interleaved configuration, multiple pipes (access control units) can simultaneously access the same VRG.
can be accessed without having to interact with the
FIG. 9 is an explanatory diagram of this (described later).

The number of elements in each vector register VR _O , VR _{1 .} . . may be variable, but for simplicity, it is basically 8. The number of actually valid elements is left over by the vector length VL. The number of VRs that make up one VRG is 256, and is specified by an 8-bit address. For element allocation, when there is one VRG, element n is made to correspond to bank n. In FIG. 8, E is an element, and the numbers therein are element numbers.

The instruction control device 19 in FIG. 7 includes a vector length register VLR, in which the value of VL is set by a control instruction. This VL indicates the number of valid elements. The memory access control unit (VSu) 18 stores the number of data indicated by VL.
Transfer between MEM11 and VRG17. Further, the arithmetic unit 20 processes the number of data indicated by VL using the same instruction.

FIG. 9 is a bank timing time chart that defines the timing for accessing the first element (element number ₀ ) of the vector register _VR for each access source (pipe, arithmetic unit). Eight timings of E ₃ , L, F ₁ , F ₂ , and F ₃ are repeated cyclically. Of these, K and L are for pipes, E ₁ or F ₁ , E ₂ or
F ₂ , E _{3 ,} and F ₃ are for the arithmetic unit, and access the VR specified by the R1, R2, and R3 parts of the instruction word, respectively. One instruction word consists of a 1-byte (8-bit) operation code section (OP) and three vector data operand sections R1, R2, and R3 (1 byte each) to be read. The operation indicated by OP is executed on the vector data for each element of the same number, and the result is written to the element of the same number of VR indicated by R1.

FIG. 10 shows another embodiment of the present invention, in which one VRG is controlled by a two-pipe memory access control device.
The control change function when handling is shown. In the same figure, 1000A and 1000B (hereinafter referred to as A,
B is omitted) are two pipes (access control part)
When a control circuit and the like are added to this, a memory access control device (VSu) 8 as shown in FIG. 7 is obtained. 1010
(Suffixes A and B are omitted as appropriate for simplicity, the same applies to other items)) is a bidirectional bus that transfers bidirectional data input and output to the memory control unit (MCu) 12 by switching gates. . 1001 is MCu
1002 is a store data register (SDR) that holds store data to MCu2, 1003 is an align circuit (ALiGN) that rearranges the data string, and 1004 is a fetch data register (FDR) that holds the fetch data from 12. The aligned register stack (ARS) 1020 is a group of vector registers.

The configuration up to this point is similar to the previously proposed configuration.
First, to explain its operation, (1) In the case of a data fetch instruction, the MCu
Data for each four elements sent from 12 enters a register 1001, is rearranged into the correct order of elements through an align circuit 1003, and then held in a stack 1004. stack 1004
The data held in is retrieved using the FiFo (first-in, first-out) method, and when bank time is obtained, VRG1020 is stored for each element.
is written to the corresponding VR. (2) In the case of a data store instruction, data is read out from the VR element by element when bank time is available and held in the stack 1004. And stack 10
The data held in 04 is retrieved in FiFo style,
The memory 11 (seventh
Register 1 after being rearranged in the order of addresses in Figure)
002 and through the bidirectional bus 1010.
Sent to MCu12.

In this example, gate logic (GL) 1005A, 1005B is added to each pipe 1000A, 1000B, and is controlled by a structure change signal 1030. Gate logic 1005 consists of a group of gates that control whether or not input data is transmitted to the output side.
When the structure change signal 1030 is 0, the gate is closed, and when it is 1, the gate is opened.
When 030 is 0, it is called 1-pipe mode, and when it is 1, it is called 2-pipe mode, and the operation of each mode will be explained.

1 pipe mode: At this time, gate logic 1
005A and 1005B are closed, stack 1004A (ARS A) is connected only to banks 0 to 3 of VRG 1020, and stack 1004A (ARS A) is connected only to banks 0 to 3 of VRG 1020.
B (ARS B) is connected only to banks 4 to 7 of VRG 1020. In this case pipe 1000
A and 1000B can execute the same instruction simultaneously.
In other words, in FIG. 9, pipes 1000A, 10
Both 00B are either K or L (one is a solid line,
VR access is started at the same time when the other side is connected (wired). The pipe 1000A handles elements 0 to 3, and the pipe 1000B handles elements 4 to 7, and writes or reads data there. The start of VR access indicates the start of access from the first bank, so there is a risk of conflict if these are the same, but if you set VR from 0 to
If divided into two groups, 3, 4 to 7, the access start banks are 0 and 4, and the latter one is 1, 2, 3, 0,
1,..., the other goes 5, 6, 7, 4, 5,..., so they never collide.

2 pipe mode: At this time, gate logic 1
Since 005A and 1005B open, stacker 10
04A and 1004B are both connected to banks 0 to 7 of VRG 1020. In this case, as shown by the solid line in FIG.
Set the bank times to be different for B (one is K and the other is L) to prevent pipes 1000A and 1000B from accessing (colliding) the same bank of VRG 1020 at the same time, and then operate both pipes independently. Execute two instructions at the same time if possible.

The advantages and disadvantages of each mode described above are as follows. In 1-pipe mode, only one instruction can be executed, but it only takes 4τ to access VR from elements 0 to 7. On the other hand, in 2-pipe mode, two instructions can be executed at the same time, but it takes 8τ to access VR from elements 0 to 7. Therefore, when the frequency of memory access instructions is high, the 2-pipe mode is more advantageous because it allows two instructions to be executed at the same time, and when the frequency of memory access instructions is low, the 1-pipe mode doubles the amount of data transferred. This will be advantageous.

Two examples of changing the structure of the hardware using the structure change signal have been described above. Next, a control section that changes the structure change signal by determining the nature of the software will be described. There are two basic ways of thinking about this control section. One is to record the instruction type and change the hardware structure based on the result (FIG. 11), and the other is to change the logic depending on the usage status of the hardware.

Figure 11 shows the structural change signal 118 required in Figure 3.
1 (300 in FIG. 3), and is based on the following conditions. (1) Record only instructions (ED instructions) that use external data as the instruction type. (2) The recording period is calculated by counting the number of instructions input to the instruction register _iRO in Figure 3, that is, the number of times the clock _CLO is turned on, and this becomes equal to a predetermined number N. up to. (3) Count the number x of ED commands during the above period, and when the counted value exceeds a predetermined number X, change the configuration in FIG. 3 to FIG. 5.

Buffer 1100 and signal line 1 in FIG.
101 and clock _CLO (signal line 1102) correspond to buffer 4, signal line 301, and clock _CLO in FIG. 3, respectively. Counter 1150 is a clock
Each time _CLO turns on, it counts up from 1 to N (assumed to be 10), and at the N+1st time, the clock _CLO
When turned on, the count value n is returned to 1. The count value n of this counter 1150 is output to a signal line 1151 as a binary number in 4 bits. 1160 is N=
n, that is, the value n of the counter 1157 is 10 (=N)
This is a circuit that detects whether the latch 11 is
61 to 1164 are set to an N value of 10 (1010 in binary) using 4 bits of a binary number, and when the output and the signal line 1151 are connected, the output 1166 of the gate 1165 is set to 1. The operations of the counter 1120 and the arrival detection circuit 1130 are similar to those described above, but the value x of the counter 1120 is set to 0 when the serialization end signal 1171 (described later) becomes 1. Reference numeral 1180 is a set/reset type latch that gives priority to set (S), and when the reset (R) input becomes 1, it is reset and the output 1181 becomes 0. However, even if the R input is 1, if the S input becomes 1, set takes priority and the output 1181 becomes 1.

The serialization control circuit 1170 is connected to the signal line 116
It is activated when signal 6 becomes 1, and prohibits the execution of subsequent instructions (does not turn on clock _CLO ) until all instructions held in the instruction register (iR) in Figure 1 are completed. When the register iR becomes empty, the serialize end signal 1171 is turned on. This operation is called instruction serialization.

Next, the overall operation will be explained. During the period when n<N (signal line 1167 is 1), buffer 1
An ED command is sent from 100, which is sent to decoder 1.
When decoded by 110, its output becomes 1, so when clock _CLO becomes 1, the output of AND gate 1111 becomes 1, and counter 1120
Count up by one. When the value x of the counter 1120 reaches the number set by the circuit 1130 (5 in this example), the set/reset type latch 1140
is set.

When n=N (10 in this example), the signal line 116
0 becomes 1. As a result, first the signal line 1167
(signal line 1166 inverted with an inverter)
becomes 0, and counting up of the counter 1120 is prohibited. Also, the serialization control circuit 117
0 is activated, the above-mentioned serialization operation is started. When this is finished, the serialize end signal 1171 is turned on.

At this time, if x<X, the output of latch 1140 is 1 (reset state), so latch 1180 is set and structure change signal 1181 is 1.
becomes. Also, if x≧X, the latch 114 is already
Since 0 is set and its output is 0, latch 1180 is reset and structure change signal 1181 becomes 0.

Furthermore, when the serialize end signal 1171 turns on at the same time as the above operation, the counter 1120 becomes 0.
is set. As a result, latch 1140 is reset and returned to its initial value, and clock _CLO is also uninhibited to begin the next N period of operation. Here, the value of latch 1180 remains unchanged for the next N periods. The structure change signal 1181 is 30 in FIG.
0 and 600 of FIG. When the signal 1181 is 1, the configuration shown in FIG. 4 is used for the next N period, and when the signal 1181 is 0, the configuration shown in FIG. 5 is used.

In addition, in FIG. 11, latches 1131 to 113
3, the outputs of 1161 to 1164 are determined by X,
It is set to output N, but this value may be changed by configuration control or OPSR (Operation Status Register).
Also, in Figure 11, X = 5 and N = 10, but if these values are small, serialization will occur frequently,
The loss caused by this becomes greater than the benefit of changing the configuration, and performance deteriorates instead. Therefore, the values of X and N need to be set to a certain degree of large value so that the loss due to serialization is gradually smaller than the benefit due to configuration change.

FIG. 12 shows an example of a control section that generates a structural control signal 1281 (1030 in FIG. 10) suitable for controlling the functions shown in FIG. 10, and is based on the following conditions.
(1) As the hardware usage status, the number r of registers actually used in the stacker 1004B (ARS B) in FIG. 10 is used. (2) The recording period is
It is assumed to be N cycles (period in which the machine cycle clock appears N times). (3) During the above period, r is the value R ₁ to R ₂ determined by the current hardware structure.
The number of times x that has occurred is counted, and if the counted value is greater than or equal to a predetermined number X, the logic in FIG. 10 is set to 2-pipe mode.

Signal line 1200 is connected to stack 1004 in FIG.
The number r of registers actually used in ARS B (ARS B) is reported. This number r is a value sent from a logic unit (not shown) that controls the circuit of FIG. 10, and uses, for example, the difference between the write (WRiTE) address and read (READ) address of the stack 1004B.

1210 and 1211 are respectively determined values
Registers holding R ₁ and R ₂ , 1212, 121
3 are circuits that detect r≧R ₁ and r≧R ₂ and output 1 when the conditions are met; 1220 and 12;
30, 1240, 1250, 1260, 127
0 and 1280 are respectively 1120 and 1 in Figure 11.
130, 1140, 1150, 1160, 117
This is the same circuit as 0,1180. However, the counter 1250 is counted up not by the clock _CLO but by the machine cycle clock, and also by the input signal COUNT UP which prohibits counting up.
iNHiBiT is supplied. Serialization control section 1
270 outputs a signal 1272 (serialization execution) indicating that serialization is being executed (from when 1261 turns on until the serialization end signal 1271 turns on). 12
82 is a signal instructing 1 pipe mode, 1283
is a signal instructing the 2-pipe mode.

Next, the overall operation will be explained. When the serialization control is finished and the counter 1250 is operating, the signal 1273 (which is the signal 1272 inverted by an inverter) becomes 1, and the AND gates 1214 and 1215 become valid. When currently operating in 1-pipe mode, signal 1282 becomes 1 and gate 1214 is enabled. In this state, the comparison circuit 1212 compares the values of r and _R1 , and if r≧ _R1 , the output of the OR gate 1216 becomes 1 and the counter 1220 counts up. Signal 1 when operating in 2-pipe mode
283 becomes 1 and gate 1215 becomes valid.
In that state, r and R ₂ are determined by the comparison circuit 1213.
The values of are compared, and if r≧R ₂ , the gate 121
The output of 6 becomes 1, and the counter 1220 counts up. The subsequent operations are similar to those shown in FIG. The structure change signal 1281 thus obtained becomes 1030 in FIG. When the signal 1281 is 0, the circuit of FIG. 10 is in the 1-pipe mode for the next N period, and conversely, when it is 1, the circuit is in the 2-pipe mode.

In Figure 12, the values at which r is compared depending on the state of 1-pipe mode and 2-pipe mode are R ₁ = 6, R ₂
= 3, and the reason is as follows. In other words, in the 1-pipe mode, r is 6
The fact that the number of times x is small means that
Stack ARS with fewer instructions to access MEM
This is because it is presumed that it is advantageous to use the 1-pipe mode for the next N period as well, since there is less overflow. The opposite is true when x is large. In the 2-pipe mode state, the fact that the number of times r becomes 3 or more x is small means that the stack ARS B is almost empty and pipe B is not operating much. Therefore, in the next N period, the 1-pipe mode is This is because it is presumed that it is more advantageous to do so. The opposite is true when x is large.

In addition, in FIG. 12, registers 1210 and 1211
The output of is set to a predetermined value, but this value may be changed by configuration control, OPSR, etc. Regarding the values of X and N, the same can be said as in the description regarding FIG.

Effects of the Invention As described above, according to the present invention, the computer itself can automatically change the structure of the hardware or firmware to suit the software. It is highly flexible and can provide optimal performance for each program even in situations where the program changes frequently, making it a more general-purpose computer. This is especially effective when running a wide variety of programs.

In addition, although only two examples are given in the embodiment, various other structural change functions and their control units are conceivable. Furthermore, by using these structural modification functions everywhere, it is possible to make the computer even more flexible.

In addition, as is clear from each of the above-mentioned examples,
When implementing the present invention, there are additional parts to the hardware, which increases the amount of hardware, but this can be solved with the development of VLSi. In other words, although the number of internal gates increases dramatically in VLSi, the number of pins that interface with the outside cannot be increased commensurately. Therefore, if the conventional design is realized with VLSi, there will be a considerable number of unused gates. Therefore, even when using a large number of gates as in the present invention, the number of pins only increases by one or a few more, and what is more, some percentage of the gates used are ones that cannot be used with the original number of pins. It has the advantage that it is only .

For example, as a simple example, if two types of structures are created in one VLSi and switched by an external signal, the number of gates will approximately double, but the number of pins will only increase by one.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional instruction control device without a structure change function, Fig. 2 is a detailed diagram of its flag control circuit, and Fig. 3 is an embodiment of the present invention applied to the above instruction control device. A configuration diagram showing an example, FIGS. 4 and 5 are explanatory diagrams showing changes in the structure of the main part, and FIG. 6 is a main part configuration showing a part added to the flag control circuit due to the structural change in FIG. 4. 7 is a schematic configuration diagram of the entire information processing device that processes multiple data at high speed, FIG. 8 is an explanatory diagram of a vector register group provided in the vector data processing device, and FIG. 9 is an explanatory diagram of the vector register group provided in the vector data processing device. FIG. 10 is a configuration diagram showing another embodiment of the present invention applied to a memory access control device provided in the vector data processing device, and FIG. 11 is a time chart showing the access timing of the vector data processing device. A configuration diagram showing an example of a control unit that generates a structure change signal based on the result,
FIG. 12 is a configuration diagram showing an example of a control section that generates a structural change signal depending on the usage status of the hardware. 1130, 1160, 1180 and 12 in the drawing
12, 1213, 1220, 1230, 126
0, 1280 is a control unit that determines the nature of the software being executed, 320, 321, 322, 323,
331, 332 and 1005A, B are functions for changing the hardware configuration, 300, 1030, 1
181 and 1281 are structural change signals.

Claims (1)

[Claims] 1. One or more types of instructions input or executed within a predetermined period are recorded in an information processing device having hardware and firmware and software for operating the same, and based on the results. It is characterized by being equipped with a control unit that determines the nature of the software that is currently being executed, and a function that changes the configuration or logic of the hardware or firmware to a form that is compatible with the software according to the determination result. Information processing equipment. 2. An information processing device that has hardware and firmware and software that operates the hardware is equipped with a control unit that records the usage status of the hardware within a predetermined period and determines the nature of the software currently being executed based on the results. An information processing device characterized by being provided with a function of changing the configuration or logic of hardware or firmware to a form compatible with the software according to the determination result.