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JPH0231403B2 - - Google Patents

Info

Publication number
JPH0231403B2
JPH0231403B2 JP55088310A JP8831080A JPH0231403B2 JP H0231403 B2 JPH0231403 B2 JP H0231403B2 JP 55088310 A JP55088310 A JP 55088310A JP 8831080 A JP8831080 A JP 8831080A JP H0231403 B2 JPH0231403 B2 JP H0231403B2
Authority
JP
Japan
Prior art keywords
signal
inspection
circuit
output
process control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55088310A
Other languages
Japanese (ja)
Other versions
JPS5713515A (en
Inventor
Juji Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8831080A priority Critical patent/JPS5713515A/en
Publication of JPS5713515A publication Critical patent/JPS5713515A/en
Publication of JPH0231403B2 publication Critical patent/JPH0231403B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00Testing or monitoring of control systems or parts thereof
    • G05B23/02Electric testing or monitoring

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Testing And Monitoring For Control Systems (AREA)

Description

【発明の詳細な説明】 この発明は、状態の変化が緩慢な制御対象を制
御するプロセス制御装置の点検回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection circuit for a process control device that controls a controlled object whose state changes slowly.

従来、この種の装置を点検する方法は、熟練し
た作業員が制御対象の安定を確認した時点で点検
の開始をさせるもので、点検中は装置に点検信号
を供給する一方、制御対象に外乱を与えないよう
に適当な方法で代りのプロセス信号を供給してや
る必要があつた。
Conventionally, the method of inspecting this type of equipment is to have a skilled worker start the inspection as soon as he/she confirms that the controlled object is stable. It was necessary to supply an alternative process signal in an appropriate manner so as not to cause

このように従来の技術は、点検が容易でなく、
点検中に制御対象に新らたな変化が生じても速か
に対応できない欠点があつた。
In this way, conventional technology is not easy to inspect;
The drawback was that even if new changes occurred in the controlled object during inspection, it was not possible to respond quickly.

この発明は、前記のような従来の問題を解決す
るためになされたもので、点検が容易に開始でき
ると共に点検中のプロセス信号に所定値以上の変
化が生じたときは、直ちに点検を中止し、かつ点
検時から通常時の動作に復帰する際のバンプレス
の切換を可能とするプロセス制御点検回路を提供
することを目的とする。
This invention was made in order to solve the conventional problems as described above, and it is possible to easily start an inspection, and also to immediately stop the inspection when a change of more than a predetermined value occurs in the process signal during the inspection. It is an object of the present invention to provide a process control inspection circuit that enables bumpless switching when returning to normal operation from inspection.

以下、この発明の一実施例を図について説明す
る。図において、コントローラ1は、プロセス制
御装置であり、点検対象のものである。このコン
トローラ1の入力であるプロセス信号PCIは、ま
ず、回路2に供給される。回路2は、プロセス信
号PCIを適当なサンプリング周期でサンプリング
して記憶する機能と、先に記憶した内容と現在の
プロセス信号PCIの内容との差をとり、その差が
所定値以下であることが自動的に確認され、かつ
点検の開始を指令する起動信号TSTが入力され
ているときは点検許可信号2aを出力する機能
と、この点検許可信号2aを出力していないとき
はプロセス信号PCIを通過させる機能と、点検時
から通常時の動作に復帰する際に内部に記憶され
ている内容を順次出力させた後にプロセス信号を
通過させる機能とを有する。点検許可信号2aが
切換回路3、切換器4−1,4−2,4−3によ
つて構成される切換装置の切換回路3に入力され
ることにより切換回路3は切換器4−1,4−
2,4−3を実際に動作させる信号3aを出力す
る。
An embodiment of the present invention will be described below with reference to the drawings. In the figure, a controller 1 is a process control device and is an object to be inspected. The process signal PCI, which is an input to the controller 1, is first supplied to the circuit 2. The circuit 2 has a function of sampling and storing the process signal PCI at an appropriate sampling period, and a function of calculating the difference between the previously stored contents and the current contents of the process signal PCI, and checking that the difference is less than a predetermined value. It is automatically confirmed, and when the start signal TST that commands the start of inspection is input, the inspection permission signal 2a is output, and when this inspection permission signal 2a is not output, the process signal PCI is passed. It has a function of sequentially outputting the internally stored contents when returning to normal operation from the time of inspection, and then passing a process signal. When the inspection permission signal 2a is input to the switching circuit 3 of the switching device constituted by the switching circuit 3 and the switching devices 4-1, 4-2, and 4-3, the switching circuit 3 switches between the switching devices 4-1, 4-2, and 4-3. 4-
It outputs a signal 3a that actually operates 2 and 4-3.

切換器4−1は、回路2を通過して来たプロセ
ス信号PCI又は点検信号発生器5の点検信号5a
を選択的にコントローラ1に供給する。コントロ
ーラ1から出力される制御信号1aは、切換器4
−2を介して記憶回路6に入力される。また、記
憶回路6の信号6aとコントローラ1の制御信号
1aは切換回路3の出力指令3aにより切換器4
−3で選択されてプロセス出力となる。
The switch 4-1 outputs the process signal PCI that has passed through the circuit 2 or the inspection signal 5a from the inspection signal generator 5.
is selectively supplied to the controller 1. The control signal 1a output from the controller 1 is transmitted to the switch 4
-2 to the storage circuit 6. Further, the signal 6a of the memory circuit 6 and the control signal 1a of the controller 1 are transmitted to the switching circuit 3 by the output command 3a of the switching circuit 3.
-3 is selected and becomes the process output.

記憶回路6は、所定のサンプリング周期で制御
信号1aをサンプリングして更新しながら記憶す
る回路で、切換器4−2が閉の場合は常時新しい
入力をサンプリングし、記憶内容と更新するが、
切換器4−2が開になつたときは、記憶した内容
を更新することなく信号6aを出力する。
The memory circuit 6 is a circuit that samples the control signal 1a at a predetermined sampling period and stores it while updating it. When the switch 4-2 is closed, it always samples new input and updates it with the stored content.
When the switch 4-2 is opened, the signal 6a is output without updating the stored contents.

動作において、非点検時、つまり通常時は切換
器4−1,4−2,4−3が図示の位置にあり、
かつ起動信号TSTが入力されていないので、コ
ントローラ1は、回路2を介してプロセス信号
PCIを入力し、これに基づき制御演算を行い制御
信号1aを切換器4−3を介してプロセスへ出力
する。
During operation, during non-inspection, that is, during normal operation, the switching devices 4-1, 4-2, and 4-3 are in the positions shown in the figure.
Since the start signal TST is not input, the controller 1 receives the process signal via the circuit 2.
The PCI is input, control calculations are performed based on the PCI, and the control signal 1a is output to the process via the switch 4-3.

一方、点検時は、まず起動信号TSTが回路2
に供給される。そして、回路2は、プロセス信号
PCIが所定値以下の変化しか示さないとき、即ち
プロセス制御系が安定しているときは、点検許可
信号2aを出力し、切換回路3より信号3aを出
力させ、切換器4−1,4−2,4−3を図示と
逆の位置にする。
On the other hand, during inspection, first the start signal TST is set to circuit 2.
is supplied to And circuit 2 is a process signal
When the PCI shows only a change less than a predetermined value, that is, when the process control system is stable, the inspection permission signal 2a is output, the switching circuit 3 outputs the signal 3a, and the switching circuit 4-1, 4- 2, 4-3 in the opposite position as shown.

これにより、点検信号発生器5の点検信号5a
は切換器4−1を介してコントローラ1に入力さ
れると共に、記憶回路6は、切換器4−2が開と
なつた時点における制御信号1aからなる信号6
aを切換器4−3を介して出力する。
As a result, the inspection signal 5a of the inspection signal generator 5
is input to the controller 1 via the switch 4-1, and the memory circuit 6 stores a signal 6 consisting of the control signal 1a at the time when the switch 4-2 is opened.
a is output via the switch 4-3.

このような点検時において、プロセス信号PCI
が変化すると、回路2は点検許可信号2aを出力
しなくなるので、切換回路3も信号3aを出力し
なくなり、切換器4−1,4−2,4−3を図示
の位置に復帰させる。つまり、コントローラ1の
点検が中止され、コントローラ1は通常時の動作
をする。
During such inspections, the process signal PCI
When this changes, the circuit 2 no longer outputs the inspection permission signal 2a, so the switching circuit 3 also no longer outputs the signal 3a, returning the switches 4-1, 4-2, and 4-3 to the illustrated positions. That is, the inspection of the controller 1 is canceled and the controller 1 operates normally.

また、点検時から通常時の動作に復帰する際は
回路に記憶されている内容を順次出力させた後に
プロセス信号を通過させる。
Further, when returning to normal operation from the time of inspection, the contents stored in the circuit are sequentially outputted, and then the process signal is passed.

以上のようにこの発明によれば点検の開始を指
示する起動信号が供給され、かつプロセス信号の
変化が所定値以下であることが自動的に確認され
ているときのみ点検を開始あるいは継続し、また
点検開始時点でプロセス装置に供給していたプロ
セス制御信号を記憶し、これを点検中は継続的に
出力するようにし、またプロセス入力信号に対
し、直列にプロセス信号に過渡変化があるか否か
を検知する回路が挿入された構成であるので、プ
ロセス制御系が安定しているのを確認して点検を
するのが簡単に実行でき、プロセス制御系が不安
定となつたときは直ちにプロセス制御装置を通常
の運転に復帰させることができ、かつ点検時から
通常時の動作に復帰する際に回路に記憶されてい
る内容を順次出力させた後にプロセス信号を通過
させることによりバンプレスの切換が可能である
などの効果がある。
As described above, according to the present invention, the inspection is started or continued only when a start signal instructing the start of the inspection is supplied and it is automatically confirmed that the change in the process signal is less than or equal to a predetermined value. In addition, the process control signal that was being supplied to the process equipment at the start of the inspection is memorized and continuously output during the inspection, and the process control signal is checked in series with the process input signal to determine if there is a transient change in the process signal. Since the configuration includes a circuit that detects whether the process control system is stable or not, it is easy to check and confirm that the process control system is stable, and if the process control system becomes unstable, the process control system can be immediately The control device can be returned to normal operation, and when returning to normal operation from the time of inspection, bumpless switching is achieved by sequentially outputting the contents stored in the circuit and then passing the process signal. This has the effect of making it possible to

【図面の簡単な説明】[Brief explanation of drawings]

図はこの発明の一実施例によるプロセス制御点
検回路のブロツク図である。 1……コントローラ、2……回路、2a……点
検許可信号、3……切換回路、5……点検信号発
生器、6……記憶回路。
FIG. 1 is a block diagram of a process control inspection circuit according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Controller, 2... Circuit, 2a... Inspection permission signal, 3... Switching circuit, 5... Inspection signal generator, 6... Memory circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 入力されるプロセス信号に従い所定の処理を
してプロセス制御信号を出力するプロセス制御装
置を点検するプロセス制御点検回路において、通
常時は、入力するプロセス信号を通過出力すると
ともに、プロセス信号を適当なサンプリング周期
でサンプリングして順次記憶しており、点検時、
先の記憶内容と現在のプロセス信号との差が所定
値以下で、かつ、起動信号が入力されているとき
点検許可信号を出力する回路、この回路の出力す
る点検許可信号により動作する切換回路、上記プ
ロセス制御装置を点検するための点検信号を出力
する点検信号発生器、通常時は、上記回路の出力
するプロセス信号を選択し、上記切換回路の動作
により切換つて上記点検信号発生器の出力する点
検信号を選択して上記プロセス制御装置へ供給す
る第1の切換器、通常時は、上記プロセス制御装
置の出力を記憶・更新し、上記切換回路の動作に
よりその記憶値を保持し、出力する記憶回路、通
常時は、上記プロセス制御装置の出力を選択し、
上記切換回路の動作により切換わつて上記記憶回
路の出力を選択して出力する第2の切換器を備
え、上記切換回路の動作時から通常時に復帰する
とき、上記回路に記憶している内容を順次上記プ
ロセス制御装置に出力した後、プロセス信号を出
力するようにしたことを特徴とするプロセス制御
点検回路。
1. In a process control inspection circuit that inspects a process control device that performs predetermined processing according to an input process signal and outputs a process control signal, normally the input process signal is passed through and output, and the process signal is It is sampled at sampling intervals and stored sequentially, and during inspection,
a circuit that outputs an inspection permission signal when the difference between the previous stored content and the current process signal is less than a predetermined value and a start signal is input; a switching circuit that operates according to the inspection permission signal output from this circuit; An inspection signal generator that outputs an inspection signal for inspecting the process control device; under normal conditions, it selects the process signal output from the circuit, switches it by the operation of the switching circuit, and outputs it from the inspection signal generator. A first switching device that selects an inspection signal and supplies it to the process control device, which normally stores and updates the output of the process control device, and holds and outputs the stored value through the operation of the switching circuit. The memory circuit normally selects the output of the process control device,
A second switch is provided which is switched by the operation of the switching circuit to select and output the output of the storage circuit, and when returning to normal operation from the operation of the switching circuit, the contents stored in the circuit are A process control inspection circuit characterized in that a process signal is output after being sequentially output to the process control device.
JP8831080A 1980-06-27 1980-06-27 Process control checking circuit Granted JPS5713515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8831080A JPS5713515A (en) 1980-06-27 1980-06-27 Process control checking circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8831080A JPS5713515A (en) 1980-06-27 1980-06-27 Process control checking circuit

Publications (2)

Publication Number Publication Date
JPS5713515A JPS5713515A (en) 1982-01-23
JPH0231403B2 true JPH0231403B2 (en) 1990-07-13

Family

ID=13939350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8831080A Granted JPS5713515A (en) 1980-06-27 1980-06-27 Process control checking circuit

Country Status (1)

Country Link
JP (1) JPS5713515A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60131873A (en) * 1983-12-15 1985-07-13 株式会社東芝 Cerqmic-metal direct bonded body and manufacture
US5561321A (en) * 1992-07-03 1996-10-01 Noritake Co., Ltd. Ceramic-metal composite structure and process of producing same

Also Published As

Publication number Publication date
JPS5713515A (en) 1982-01-23

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