JPH0231271A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To perform disconnection/connection between processors and a system bus in accordance with an exclusion/inclusion signal received from outside by adding a system bus interface to each processor contained in a multiprocessor system. CONSTITUTION:When the external exclusion/inclusion signal is inputted to an interruption signal production part 21 of the system bus interface added to each processor in a multiprocessor system, an exclusion/inclusion request signal is outputted to a system bus. Each normal processor that detected the exclusion/inclusion request signal sends an exclusion/inclusion command to a gate control part 26 via the system bus and at the same time updates the system control resources information. Therefore no access is given to the disconnected processors at all and at the same time the processors can be included into the system without setting this system in an off-line state.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention relates to a multiprocessor system equipped with a plurality of processors that share a system bus, and particularly relates to an online system that targets the processors in the system. Regarding maintenance methods.

(Prior Art) In this type of multiprocessor system, when a fault occurs in any processor in the system, that processor (faulty processor) is disconnected from the system bus. The system is operated in this state (degenerate state).

In addition, in the system described in 1.1 above, in order to exclude a desired processor from the system for maintenance, inspection, etc., the operator operates to exclude the processor using a switch (exclusion switch) provided corresponding to the processor to be excluded. It is now possible to give instructions. When this switch is turned on, an exclusion signal is generated, and the excluded processor is disconnected from the system bus in response to this exclusion signal. However, this state cannot be recognized by the operating system (OS) that manages the system, and therefore, the OS (a processor operating under the management mode) may wastefully access a processor that has been disconnected from the system. In this case, although the OS can determine that the processor attempting to access is abnormal, it cannot determine that the processor has been disconnected from the system. At this time, o
s deletes the registration of the abnormal processor from the resource management information for managing system resources by abnormal processing, and excludes the processor from the system management resources.

Now, in the multiprocessor system described in -F, there is a switch for instructing the incorporation so that the processor that is finally excluded from the system can be incorporated into the system due to the occurrence of a processor failure or an instruction to exclude the processor by an operator's operation. switches) are available for 8 processors. This built-in switch is generally turned on after the system is offline. When the integration switch is turned on, an integration signal is generated, and the processor to be integrated is connected to the system bus in response to this integration signal.

Then, in this state, the system is initialized, and the system is returned to the online state (111). In addition, if you are online, 1L. ;ill! When a processor is incorporated, the processor cannot be accessed from other processors because it is not included in the system management resources.

(Problems to be Solved by the Invention) As mentioned above, conventionally, even if the target processor is disconnected from the system bus for maintenance or inspection of the processor in a multiprocessor system, it is still not incorporated into the system management resources. Therefore, there was a problem in that access to the same processor occurred. In addition, in order to incorporate a processor that has been disconnected from the system bus into the system, the system must be temporarily placed in an offline state, which poses a problem of lowering the operating efficiency of the system.

Therefore, the first problem to be solved by the present invention is to enable the processor in a multiprocessor system to be excluded from system management resources when the processor is disconnected from the system bus. A second object of the present invention is to enable a processor to be incorporated into a system without taking the system offline.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a system bus interface for each processor in a multiprocessor system, and provides a system bus interface for each processor in a multiprocessor system, and provides a system bus interface for each processor in accordance with an externally applied exclusion signal or inclusion signal. Interrupt signal generation means for outputting an exclusion request interrupt signal or an integration request interrupt signal to the system bus, and an exclusion command for instructing exclusion of the corresponding processor from the system or an embedded command for instructing integration into the system. A gate control means is provided to control disconnection or connection between the corresponding processor and the system bus, and a gate control means is provided to control disconnection or connection between the corresponding processor and the system bus. The processor that receives the integration request interrupt signal updates the system resource management information, and also sends an exclusion command or integration command via the system bus to the gate control means of the system bus interface corresponding to the processor to be excluded or integrated. The feature is that an exclusion/inclusion management means for transfer is provided.

(Operation) According to the configuration described in item 1, when a processor failure occurs, ・1
N! When an exclusion signal is given from the outside, this is detected by the normal processor, and the detection processor notifies the gate control means of the system bus interface corresponding to the processor to be excluded of an exclusion command, and this command is Accordingly, the excluded processor is disconnected from the system bus. At this time, the system management resource information is updated by the detection processor, and the exclusion target processor is excluded from the system resources. Therefore, there is no possibility that other processors may access the processor that has been disconnected from the system bus. Furthermore, when an embedding signal is given from the outside, this fact is detected by the processor running online, and the detection processor notifies the embedding command to the gate control means of the system bus interface corresponding to the processor to be embedded. , the processor to be incorporated is connected to the system bus in response to this command. At this time, the system management resource information is updated by the detection processor, and the processor to be integrated is integrated into the system resources. That is, according to the above configuration,
A processor can be incorporated into the system without taking the system offline.

(Embodiment) FIG. 1 shows a block configuration of a multiprocessor system according to an embodiment of the present invention. In the figure, 11 is a system bus, 12-1, 12-2 and 12-n are processors that share the system bus 11, and 13 is a common control unit (system control unit). The common control unit 13 is the processor 1
2-1 to 12-n are connected, and the processor 12-1-12
-n transmission of control signals between processors 12-1 to 1;
2-n and a main memory (not shown), and is configured to control separation of the processors 12-1 to 12-n from the system and integration into the system. . The processors 12-1=12-n each have independent electric power fis 14-1 to 14-n, and the common control unit 13 also has an independent power source 15.

The common control unit 13 connects the system bus 11 and the processor 12
-1= system bus interfaces 20-1 to 20-n for connecting to 12-n. These interfaces 20-1 to 20-n have the same basic internal configuration except for the processors to be controlled. Therefore, in FIG. 1, only the configuration of the interface 20-1 corresponding to the processor 12-1 is shown.

In the system bus interface 20-1, 21 is an interrupt signal generation unit that outputs an interrupt signal to the system (system bus 11) in response to an external processor exclusion 2 installation instruction, and 22 is a processor excluded from the system. A built-in signal 23 is externally given to the interrupt signal generation unit 21 to instruct to incorporate the processor into the system, and 23 is an incorporation signal given to the interrupt signal generation unit 21 from the outside to instruct to exclude the processor incorporated in the system from the system. This is the exclusion signal given to 24.25
26 is an exclusion or inclusion command given from the system bus 11, or a signal 27 to be described below. A gate control section 27 that controls the three-state gates 24.25 accordingly is a signal for requesting the gate control section 26 to put the three-state gates 24.25 into the 11-impedance state. 28 is an online (O) indicating that the processor 12-1 is in operation.
NLINE) signal 29 is a gate that outputs the exclusion signal 23 as a signal 27 during the period when the online signal 28 is inactive.

-h, 31 is the output driver (output gate) of the processor 12-1, and 32 is the manual driver (output gate) of the processor 12-1.
input gate). The output of the output driver 31 is connected to the input of the 3-state gate 24 (in the system bus interface 20-1), and the input of the input driver 32 is connected to the output of the 3-state gate 25 (in the system bus interface 20-!). ing.

Next, the operation of the configuration shown in FIG. 1 will be explained with reference to the flowcharts shown in FIGS. 2 to 4.

First, during online operation of the system shown in FIG. 1, one of the processors 12-1 to +2-n,
For example, assume that some kind of hardware failure has occurred in the processor 12-1. When the processor 12 detects that a hardware failure has occurred in its own hardware at step Sl in the flowchart of FIG. The occurrence of the failure is notified to other processors 12-2 to 12-n via the bus interfaces 20-2 to 20-n (step S2).
.

Among the processors 12-2 to 12-n, the processor 12
The processor, for example, the processor 12-2, which has received the notification of the failure occurrence from the processor 12-1, outputs a message to indicate to the user (operator) that the failure has occurred in the processor 12-1, stores the failure information in a disk device, etc. After performing the processing (step 5ll of the flowchart in FIG. 2),
Exclusion processing (step S12) is performed to exclude the failed processor I2-1 from the system. In this exclusion process, the processor 12-2 determines whether a failure has occurred based on system resource management information (system resource management information) managed by an O3 (operating system) not shown.
The registration information of the processor 12-1 is deleted and the processor 12-1 is excluded from the system resources. The processor 12-2 also sends the processor 12-2 to the gate control unit 26 in the system bus interface 20-1 (corresponding to the failed processor 12-1) via the system bus 11.
1 is output from the system (system bus 11). When the gate control unit 26 receives this exclusion command from the system bus 11,
The three-state gates 24 and 25 are set to a high impedance state, and the failed processor 12-1 is electrically disconnected from the system bus 11. This allows processor 12
-1 is excluded from the system.

Next, it is assumed that an active exclusion signal 23 is externally applied to the system bus interface 20-1. This exclusion signal 23 is given, for example, by an operator turning on an exclusion switch (not shown) for instructing exclusion prepared in correspondence with the processor 12-1, and is applied to the interrupt signal generation unit 21 and the gate 29. Man-powered. An online signal 28 is also manually supplied to the gate 29. The gate 29 prohibits outputting the exclusion signal 23 as the signal 27 when the online signal 28 is active, that is, when the excluded processor 12-1 is operating online.

That is, when the processor 12-1 is in an online state, the signal 27 does not become active even if an active exclusion signal 23 is applied from the outside. This signal 27 is input to the gate control section 2B. The gate control section 26 controls the three-state gate 24.2 when the signal 27 is active.
5 into a high impedance state. However, gate control 26 refrains from setting tri-state gates 24, 25 to a high impedance state when signal 27 is not active as described above. Therefore, even if the exclusion signal 23 is applied from the outside while the processor 12-1 is operating online, there is no risk that the processor 12-1 will be suddenly disconnected from the system bus 11.

Now, when the interrupt signal generation unit 21 receives an active exclusion signal 23 from the outside, it outputs an interrupt signal (exclusion request interrupt signal) to the system bus 11 requesting exclusion of the processor. Among the processors 12-1 to 12-n, the processor that receives the exclusion request interrupt signal (from the interrupt signal generator 21) on the system bus 11, for example, the processor 12-2, performs the process according to the flowchart in FIG. 3(a). Execute the interrupt handling routine shown. In this routine, processor +2-2 waits for the task being processed by the exclusion designated processor 12-1 to finish when the interrupt is accepted (step 521), and then performs the same exclusion procedure as when notifying the fault occurrence from the faulty processor. Perform processing (step 5)
22). As a result, the processor 12 under the management of O8
-2, the system resource management information is updated and the exclusion designated processor 12-1 is excluded from the system resources.

In addition, the gate control unit 26 controls the 3-state gate 24
．． 25 is set to a high impedance state, and the exclusion designated processor 12-1 is disconnected from the system bus 11. Note that it is also possible for the exclusion designation processor 12-1 itself to receive an interrupt signal from the interrupt (d number generation unit 21) and perform exclusion processing for itself.

By the way, in this embodiment, if the processor to be excluded has already been excluded from the system, the exclusion signal 23 targeting the processor and the corresponding interrupt signal from the interrupt signal generation unit 21 are The hardware is configured so that it is not output. Such a configuration can be easily realized using existing technology. If such a hardware configuration is not applied, the interrupt routine shown in FIG. 3(b) may be executed instead of the interrupt processing routine shown in FIG. 3(a). In this routine, it is first checked whether the processor specified for exclusion has already been excluded (step 531). If not excluded, step S21 in FIG. 3(a). Step S32 similar to S22. S33 is performed, and if it is excluded, the process ends.

As mentioned above, processors that are removed from the system due to the occurrence of a failure such as f→ or by an operator instruction,
For example, the processor 12-1 already has a 3-state game
It is electrically isolated from the system bus 11 by lines 24 and 25. Therefore, by cutting off the power supply 14-1 of the processor 12-1 in this state, the processor 12-1 can also be physically removed.

Now, when a processor that has been excluded from the system, for example, processor 12-1, is to be incorporated into the system, an active integration signal 22 is input from the outside to the system bus interface 20-1 in the same way as the exclusion signal 23. This built-in signal 22 is manually input to the interrupt signal generation section 21 . When the interrupt signal generation unit 21 receives an active built-in signal 22 from the outside, the system bus!
1-I- outputs an interrupt signal (integration request interrupt signal) requesting processor incorporation. As a result, the processor receiving this interrupt signal, for example processor 12-
2, the interrupt processing routine shown in FIG. 4(a) is executed, and the processor incorporation processing (step S
41) is executed. In this processor incorporation process, the system resource management information is updated by the processor 12-2 under the management of O8, and the incorporation designated processor +2-1 is incorporated into the system resources. In addition, an embedded command is issued from the processor 12-2, and the command is sent via the system bus 11 (to the embedded designated processor 1).
System bus interface 20-1 corresponding to 2-1
) is manually operated by the gate control section 26.

As a result, the gate control unit 26 controls the 3-state gate 24
25 is released from the high impedance state to an enabled state, and the built-in designated processor 12-1 is electrically connected to the system bus 11. As a result, the installation process in the online state of the system is completed.

By the way, in this embodiment, if the processor to be installed is already installed in the system, the installation signal 22 targeting the processor and the corresponding interrupt signal from the interrupt signal generation unit 21 are The hardware is configured so that it is not output. If such a hardware configuration is not applied, the configuration shown in Figure 4(a)
Instead of the interrupt processing routine shown in FIG. 4(b), the interrupt routine shown in FIG. 4(b) may be executed.

[Effects of the Invention] As detailed above, according to the present invention, when a processor failure occurs or when an exclusion signal is given from the outside, the excluded processor is not only disconnected from the system bus, but also removed from the system bus. Since this processor is excluded from resources, there is no possibility that other processors will access this processor. Further, according to the present invention, when an integration signal is given from the outside, this fact is detected by the processor running online, and the detection processor integrates the integration target processor into the system resource, and the detection processor also integrates the integration signal into the system resource. In response to the installation command, the processor to be installed is connected to the system bus, and the processor can be installed into the system in an online state.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a flowchart showing the procedure for excluding a processor when a processor failure occurs, and FIG. FIG. 4 is a flowchart showing a processor exclusion processing procedure. FIG. 4 is a flowchart showing a processor integration processing procedure based on an external integration signal. 11... System bus, 12-1 to 12-n... Processor, IEI,] 4-n, l 5... Power supply,
20-1 to 2O-n-...System bus interface, 21...Interrupt signal generation section, 22...Built-in signal, 23...Exclusion signal, 24.25...3-state gate, 2G... - Gate control section, 28...online signal (ONL INE), 29... gate (exclusion signal transmission means). Applicant's representative Patent attorney Takehiko Suzue <Process 12-1><Process12-2> Figure (b)

Claims (3)

[Claims] (1) In a multiprocessor system including a plurality of processors sharing a system bus, a system bus interface is provided corresponding to each of the plurality of processors and forms an interface between the corresponding processor and the system bus, A gate means for electrically connecting/disconnecting the processor from the system bus, an externally applied exclusion signal for instructing exclusion of the corresponding processor from the system, or a gate means for electrically connecting/disconnecting the processor from the system bus; Interrupt signal generation means for receiving an externally applied integration signal for instructing integration and outputting an exclusion request interrupt signal or an integration request interrupt signal to the system bus, and for instructing removal of the corresponding processor from the system. a system bus interface having a gate control means for controlling the gate means in response to an exclusion command or a built-in command for instructing integration into the system; The processor that receives the occurrence notification, the exclusion request interrupt signal from the interrupt signal generating means, or the integration request interrupt signal from the interrupt signal generating means updates the resource management information for managing system resources, and also updates the exclusion or A multi-purpose processor comprising: exclusion/incorporation management means for transferring the exclusion command or inclusion command via the system bus to the gate control means of the system bus interface corresponding to the processor to be incorporated. processor system. (2) providing an exclusion signal transmission means for transmitting the exclusion signal given to the interrupt signal generation means of the system bus interface to the gate control means of the interface only when the processor to be excluded is not in an online operating state; When the exclusion signal is transmitted to the gate control means by the exclusion signal transmission means, the exclusion target processor is separated from the system bus by controlling the gate means by the gate control means. A multiprocessor system according to claim 1. (3) The configuration is such that power is supplied independently to the plurality of processors, and when any of the plurality of processors is removed from the system, the power supply to the target processor is cut off. A multiprocessor system according to claim 1 or 2.