JPH0230929Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a reset circuit, and more particularly, to a reset circuit that initializes the internal circuitry of an integrated circuit by generating a reset signal using a signal supplied from outside the integrated circuit.

BACKGROUND OF THE INVENTION In recent years, an increasing number of electrical devices are equipped with microcomputers or integrated circuit control circuits to control various operations. Since the internal state of such a control circuit is undefined when the power is turned on, initial settings are performed after the power is turned on to prevent the control circuit from malfunctioning. Therefore, in the integrated circuit of the conventional control circuit, one pin was independently provided as a reset terminal, and a reset signal was supplied to this pin to initialize the control circuit.

Problems that the invention aims to solve: The conventional control circuit integrated circuit described above requires one pin as a reset terminal, which increases the number of pins and requires another pin for control signal output. However, there were problems such as the possibility of not being able to add more output pins.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reset circuit that solves the above problems by using a pin as a reset terminal in common with an output pin.

Means for Solving the Problems The present invention provides a delay system that outputs a signal generated by the operation of the built-in circuit of an integrated circuit to the outside, is connected to a terminal from which an external signal is received, and delays the signal supplied from the terminal. a flip-flop which is set by a signal from the delay means and reset by a signal generated by the operation of the built-in circuit; and a gate circuit which generates a reset signal from the signal from the delay means and the output signal of the flip-flop and supplies it to the built-in circuit. An embodiment thereof will be described below with reference to the drawings.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention. In the figure, a part surrounded by a broken line shows a part of the integrated circuit 1 that includes a control circuit, and the circuit of the present invention is provided inside the integrated circuit 1. Terminal 2 is a power supply terminal within integrated circuit 1, and terminal 2 is connected to data terminal D of D-type flip-flop 3. Terminal 4 also receives a control signal from a control circuit (not shown), which is a built-in circuit, such as a motor control signal that instructs to drive the motor at L level and stop the motor at H level, and which is at H level when the power is turned on. This terminal 4 is an input terminal for inverters 5 and 6 that serve as loads for the buffer and control circuits connected in series.
Clear terminal CLR of flip-flop 3 through
It is connected to the. Further, an output terminal of the inverter 5 is connected via an inverter 7 to a terminal 8 which is an input/output terminal of the integrated circuit 1 and is connected to, for example, a motor.

Apart from the inverter 7, the terminal 8 is connected to the clock terminal CK of the flip-flop 3 and the NAND circuit (gate circuit) 1 via an inverter 9 which is a delay means.
The Q output terminal of flip-flop 3 is connected to the other input terminal of NAND circuit 10, and the output terminal of flip-flop 3 is connected to terminal 11 for supplying a reset signal to the control circuit. It is connected to the.

When the integrated circuit 1 is powered on, the signal a input from the control circuit to the terminal 4 is at H level as shown in FIG. 2A. Therefore, the terminal 8 to which the signal b obtained by inverting the signal a by the inverters 5 and 7 is supplied is slightly delayed by the inverters 5 and 7, becomes H level as shown in FIG. 2B, and is connected to the terminal 8. The motor (not shown) is in a stopped state. If the terminal 8 is forcibly brought to the L level for a time sufficiently shorter than the time required for the motor to start (from time t ₁ to t ₂ ), the signal c output by the inverter 9 will be outputted at the second level with a slight delay. As shown in FIG. 2C, it becomes H level. During the H level period of this signal c, the flip-flop 3 latches the voltage (H level) at the data terminal D and outputs the signal d shown in FIG. _2D from its Q terminal. After a delay, signals c and d at H level are both supplied to NAND circuit 10, and NAND circuit 10 generates reset signal e at L level shown in FIG. 2E. This reset signal e is supplied to the control circuit from the terminal 11, and the control circuit is initialized.

Thereafter, when the control circuit is activated and the motor control signal input to the terminal 4 becomes L level at time _t3 , the signal b at the terminal 8 becomes L level slightly later than this, and the motor is started.
Further, the signal d becomes L level with a slight delay from time t ₃ by the delay time of the inverters 5 and 6, and the signal c obtained by inverting the signal a by the inverters 5, 7, and 9 becomes H level with a slight delay from the signal d. level. Therefore, the signal e output from the NAND circuit 10 is at time t ₃
Thereafter, it continues to be at the H level and the control circuit is not reset.

In this way, the control circuit within the integrated circuit 1 can be initialized by forcibly setting the terminal 8 to the L level from the outside, and after the control circuit is activated,
This terminal 8 becomes an output terminal for a control signal. In other words, the terminal 8 can be used commonly as a reset terminal and an output terminal of the integrated circuit 1, and the number of pins of the integrated circuit 1 can be reduced by one.

Note that if the fan-out of the control circuit is small, there is no need to provide the inverters 5 and 6.
A buffer amplifier may be provided instead of the inverter 7. Further, the terminal 4 may be a terminal to which a control signal is received from another control circuit external to the integrated circuit 1. Furthermore, if the control signal is an inverted version of signal a, a buffer amplifier may be used instead of inverter 9 as a delay means to delay the fall (or rise) of signal c from the rise (or fall) of signal d. , but is not limited to the above embodiments.

Effects As mentioned above, the reset circuit according to the present invention outputs a signal generated by the operation of the built-in circuit of an integrated circuit to the outside, is connected to a terminal from which an external signal is received, and delays the signal supplied from the terminal. a flip-flop that is set by a signal from the delay means and reset by a signal generated by the operation of the built-in circuit; and a gate that generates a reset signal from the signal from the delay means and the output signal of the flip-flop and supplies it to the built-in circuit. Since it is a circuit, it is possible to initialize the built-in circuit by supplying a signal from the outside to the terminal, and after the built-in circuit is activated, the signal of the built-in circuit can be output from this terminal, and the terminal can be used as the reset terminal of the integrated circuit. It has the advantage that it can be shared as an output terminal, reducing the number of pins in the integrated circuit by one.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the circuit of the present invention;
The figure is a signal waveform diagram of each part of the circuit shown in the first figure. 1... integrated circuit, 2, 4, 8, 11... terminal,
3...Flip-flop, 5, 6, 7, 9...Inverter, 10...NAND circuit.

Claims (1)

[Scope of utility model registration request] A delay means is connected to a terminal that outputs a signal generated by the operation of the built-in circuit of an integrated circuit to the outside and receives a signal from the outside, and delays the signal supplied from the terminal, and a signal from the delay means is set. A reset circuit comprising a flip-flop which is reset by a signal generated by the operation of the built-in circuit, and a gate circuit which generates a reset signal from the signal from the delay means and the output signal of the flip-flop and supplies it to the built-in circuit.