JPH02308607A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To decrease parasitic capacitance and to obtain a high gain frequency characteristic by providing a series body comprising a resistive load and three FETs between one power supply and other power supply, connecting the capacitor in parallel with a power FET and connecting a radio frequency signal to ground. CONSTITUTION:A load resistor 11, FRTs 31-33 and an RF short-circuit capacitor 12 are connected between power supplies VDD and Vss in series. A drain of the FET 31 is used as an output terminal 13, a gate is used as an input terminal 14, a source connects to a drain of the FET 32 and a gain control voltage VACC is applied to a gate. The capacitor 12 and the PET 33 are connected between a source of the FRT 32 and the Vss, the gate and source are connected and used as a current source. Through the constitution abive, the capacitor 12 short-circuits the radio frequency signal to vary the source-drain resistance of the FET 32 and the source resistance of the FET 31 is varied equivalently to vary the gain. Through the constitution above, the amplifier circuit having the same gain control function as that of a differential amplifier circuit and a broad band gain frequency characteristic is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an amplifier circuit, and in particular to a field effect transistor (
This invention relates to a gain control (AC) amplifier circuit using FET).

[Conventional technology]

As a conventional AGC amplifier circuit, there is a differential type circuit shown in FIG. Two FETs 31 and 32 connected in series
, or use two sets of dual-gate F'ETs, connect the sources of these two sets of F'ETs 32 to each other, and connect them to the drain terminal of FET 33, which acts as a current source, and connect the drain terminals of ETs 31 and 32 connected in series. Load resistance 1 at the end
1 is connected, and this connection is used as an output terminal OUT. Of the FETs 31 and 32 connected in series, the gate of FET 32 on the current source side is used for gain control (VAGC terminal).

[Problem that the invention attempts to solve]

The conventional AGC amplifier circuit mentioned above uses a differential type circuit, so it has a large number of elements and a complicated circuit layout, which increases the wiring capacitance and reduces the gain at high frequencies, making it difficult to achieve a wide band. There are drawbacks that make it difficult.

It is an object of the present invention to provide an amplifier which solves the above-mentioned drawbacks and which, while retaining the advantages of a differential circuit, can reduce parasitic capacitance with a simple configuration, reduce the area of one circuit, and obtain high gain frequency characteristics. Our goal is to provide the following.

[Means to solve the problem]

The configuration of the amplifier circuit of the present invention is that - between the power source and another power source,
Resistive load, 1st. Second. A series body of third field effect transistors is provided, the connection point between the load and the first field effect transistor is used as an output, the gate of the first field effect transistor is used as an input, and the second field effect transistor is connected to the second field effect transistor. The gate of the effect transistor is used as a gain control input, and the third
A capacitor is connected in parallel to the third field effect transistor, and the gate of the third field effect transistor is connected to the other power source.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an amplifier circuit according to a first embodiment of the present invention.

In FIG. 1, the amplifier of this embodiment has VDDi! The amplifier circuit has a load resistor 11, first to third FETs 31, 32, 33, and an F short capacitor 12 between the source and the VSS power supply, and the load resistor 11 is connected between the VDD power supply terminal and the first The drain end of the first FET 31 is used as the output terminal 13, the gate end is used as the input (IN) terminal 14, and the first FET 31 is connected to the drain end of the FET 31.
The source end of the second FET 32 and the drain end of the second FET 32 are connected to each other, the gain control voltage VAGC is applied to the gate end of the second FET 32, and the voltage between the source end of the second F'ET 32 and the VSS power supply end is applied to the gate end of the second FET 32. , RF short capacitor 12
and the 30th FET 33 are connected, and the gate and source end of the 30th FET 33 are connected to use it as a current source.

By adopting this configuration, the DC current and DC potential can be maintained exactly the same as in the conventional differential type circuit, and the QRF is shorted by the capacitor 12, and the resistance between the drain and the north of the second FET 32 is changed. , isometrically the first FE
The gain can be varied by changing the source resistance of T31. In addition, since the operating current is determined by the third FET 33, which serves as a current source, the operating current of the first FET 31, which has an amplification function, is kept constant even when gain control is performed. It has both advantages.

The resistor 11 in FIG. 1 does not necessarily have to be a resistor, and may be any element such as a transistor as long as it can serve as a resistive load, as will be described later with reference to FIG.

FIG. 2 is a circuit diagram showing an amplifier circuit according to a second embodiment of the present invention.

In FIG. 2, the first to fourth pg'r3t.

32, 33, 21, and the RF short capacitor 12, and the fourth FET 21 is connected to Von' [the original end and the first FE
The fourth FET21 is connected between the drain end of T31 and the fourth FET21.
This is a PET load circuit with the load as the fourth FET21.
The gate potential of VDD power supply terminal and Vss? [The distance between the original ends can be given by resistance division of 40.41 series resistors. The other circuit configurations are the same as in the first embodiment. FET
By using it as a load, there is an advantage that a larger RF gain can be achieved than in the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, the capacitor is connected to the current source F.
By connecting in parallel with ET and grounding l(, F,
Compared to a differential amplifier circuit, it has a simpler configuration, has the same gain control function, has a smaller circuit area, and has the advantage of being able to obtain wideband gain frequency characteristics by reducing parasitic capacitance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an amplifier circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing an amplifier circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a conventional amplifier circuit. It is a circuit diagram.

Claims (1)

[Claims] A resistive load and a series body of first, second, and third field effect transistors are provided between one power source and another power source, and the connection point between the load and the first field effect transistor is used as an output. , the gate of the first field effect transistor is used as an input, the gate of the second field effect transistor is used as a gain control input, a capacitor is connected in parallel to the third field effect transistor, and the third field effect transistor is An amplifier circuit characterized in that a gate of an effect transistor is connected to the other power source.