JPH02304971A - Semiconductor device of master slice system - Google Patents

Abstract

PURPOSE:To enhance gate usage efficiency by providing a capacity element for adjusting the amount of delay or that for coupling. CONSTITUTION:A capacity element for adjusting the amount of delay or that for coupling is provided. That is, a capacity element C is formed by a gate electrode 7, a dielectric film 6, and a semiconductor substrate 3 (especially a semiconductor region 5), a large number of capacitor elements C are arrayed within a capacity array 2, and they are used for adjusting the amount of delay, thus eliminating the need for using a large number of gates for delay or for capacity element for coupling. Therefore, it becomes possible to enhance gate usage efficiency.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B1 Overview of the invention C1 Background art [Figs. 14 and 15] D0 Problems to be solved by the invention E3 Means for solving the problems F1 Effects G. Examples [First Figures 4 to 13] a. First embodiment [Figures 1 to 3] b. Second embodiment [Figures 4 to 9] C1 Third embodiment [Figures 10 to 13] Figure] H1 Effects of the invention (A, industrial application field) The present invention relates to a master slice type semiconductor device, and particularly to a master slice type semiconductor device that can improve gate usage efficiency.

(B. Summary of the Invention) The present invention provides a master slice type semiconductor device, in which a capacitive element for adjusting delay amount or a capacitive element for coupling is provided in order to increase gate usage efficiency.

(C. Background Art) [Figs. 14 and 15] There are two types of gate arrays: a channel type as shown in Fig. 14 and a sheave gate type.

In the channel type, channel regions b, b, . . . (currently just empty regions) for forming wiring are provided between a plurality of rows of cell arrays a, a, . Seave gates have a large number of cells arranged in the channel area as well. In both cases, a large number of basic MOS elements c, c, etc. as shown in Fig. 15 are arranged regularly, and various circuits (mainly logic circuits) can be configured with the basic MOS elements according to the user's requirements. This is what I did. In FIG. 15, the solid line indicates the gate electrode, the broken line indicates the semiconductor region that will become the source, drain, and channel, and the small circle indicated by the broken line indicates a functional location where a contact hole for taking out the electrode will be formed. shows. d is a substrate contact portion for electrically taking out the n-type semiconductor well in which the p-channel MOS basic element is formed, and e is a substrate contact portion for taking out the p-type semiconductor well in which the n-channel MOS basic element is formed.

In such a master slice type semiconductor device, when creating a logic circuit by combining gates made of M and 03I transistors, a delay circuit that delays signals, clock pulses, etc. by a predetermined time is very often required. . Conventionally, the delay circuit has been constructed of an inverter using a gate made of a MOS transistor.

In addition, conventionally, the basic MOS elements of gate arrays were only MOS transistors and contact portions d and e for exposing substrate electrodes, as shown in FIG. 15 (which was not suitable for analog circuits). This is because analog circuits require a large number of capacitive elements.Therefore, gate arrays were used only when creating digital circuits.

(D. Problem to be solved by the invention) By the way, if the delay circuit is configured with an inverter, the MOS basic elements used for the inverter cannot be used for the logic circuit, and as a result, the gate usage efficiency is low. There was a problem.

In addition, there is a need for semiconductor devices that have a mix of digital and analog circuits, and although gate arrays are not suitable for forming analog circuits because they do not have capacitive elements, as mentioned above, there is still a need to form analog circuits. There may be cases where this is not the case. In such a case, conventionally, a MOS capacitor element using a gate has to be used. Therefore, in this case as well, the MOS basic element used in place of the capacitive element cannot be used in the logic circuit, resulting in a problem of low gate usage efficiency.

The present invention has been made to solve these problems, and an object of the present invention is to improve the gate usage efficiency of a master slice type semiconductor device.

(E. Means for Solving the Problems) In order to solve the above-mentioned problems, the master slice type semiconductor device of the present invention is characterized in that a capacitive element for adjusting a delay amount or a capacitive element for coupling is provided.

According to the master slice type semiconductor device of the present invention, there is a capacitive element for adjusting the delay amount or a capacitive element for coupling. Since there is no need to allocate multiple gates for this purpose, gate usage efficiency can be increased.

(G. Embodiment) [FIGS. 1 to 13] Hereinafter, a master slice type semiconductor device of the present invention will be described in detail according to the illustrated embodiment.

(a, First Embodiment) [FIGS. 1 to 3] FIGS. 1 and 2 show a first embodiment of a master slice type semiconductor device of the present invention, and FIG. 1 is a plan view. FIG. 2 is a sectional view showing a capacitive element. In this embodiment, the present invention is applied to a channel type master slice type semiconductor device.

In the drawings, 1, l, ... are cell arrays, 2.2,
. . . is a capacitive element array formed in the channel region, in which capacitive elements are arranged as shown in FIG.

3 is a p-type semiconductor substrate, 4 is a field insulating film formed by selectively oxidizing the surface portion of the semiconductor substrate 3, and 5 is a p-type semiconductor substrate;
is a p+ type semiconductor region formed on the surface portion of the semiconductor substrate 3, 6 is a gate insulating film serving as a dielectric film, and 7 is a gate insulating film formed on the p° type semiconductor region 5 via gate insulator 1]I6. The gate electrode 8 is a glabella insulating film covering the surface of the semiconductor substrate 3.

A capacitive element C is formed by the gate electrode 7, the dielectric film 6, and the semiconductor substrate 3 (particularly the semiconductor region 5). Such a capacitive element C is a capacitive array 2.2...
A large number of them are arranged inside, and can be used for adjusting the amount of delay. Specifically, since one electrode of each capacitive element C is grounded, the signal transmitted by the capacitive element C can be delayed by connecting the other electrode to the signal transmission line. The amount of delay can be increased by increasing the number of capacitive elements C connected to one signal line.

Therefore, it is no longer necessary to construct an inverter using the MOS basic elements in the cell arrays 1.1, . . . and to delay signals using the inverter. Therefore,
All of the MOS basic elements in the cell array 1.1, . This conventional problem can be solved.

In FIG. 2, numeral 9 will be formed later on the glabellar insulating film 8 (it is not formed at the moment. However, it may be more accurate to say that there is a possibility that it will be formed, rather than that it will be formed. ) Contact hole, 10 is a wiring film formed on the surface of the glabellar insulating film 8, 11 is a glabellar insulating film formed on the surface of the glabellar insulating film 8, 12 is a contact hole formed in the interlayer insulating film 11, 13 is an interlayer This is a second wiring layer formed on the surface of the insulating film 11.

FIG. 3 is a plan view showing an example of the formation of the first wiring layer (wiring example), in which a portion marked with an x where a portion 9 where a contact hole may be formed overlaps with the wiring layer 10 is shown. , a portion where the capacitive element C is connected to the wiring layer 10.

According to the present master slice type semiconductor device, a signal can be delayed using a capacitive element formed in a portion that is originally a channel region. Moreover, the region where the capacitive element is formed can be used as it is as a channel region.

Therefore, gate usage efficiency can be significantly increased.

(b, Second Embodiment) [Figures 4 to 9] Figures 4 and 5 are for explaining the second embodiment of the master slice type semiconductor device of the present invention. 5 is a plan view, and FIG. 5 is an enlarged sectional view taken along line V-V in FIG. 4.

In this embodiment, a capacitive element is formed at a substrate contact portion. That is, in the past, the substrate contact portion was literally only capable of making substrate contacts, but each area had an area that could accommodate a large number of contacts, such as four. However, in reality it is sufficient to make one or two contacts. Therefore, in this embodiment, a MOS capacitor element is formed by forming a gate electrode, which was not previously there, in a part of the area where the substrate is contacted. A capacitive element for quantity adjustment can be formed without increasing the chip area, and the present invention can be applied not only to channel type devices but also to sea-of-gate type devices.

In the drawings, 14 is a semiconductor substrate, 15 is a p-type semiconductor well, 16 is an n-type semiconductor well, and 17 is a semiconductor substrate 14.
18 is a gate insulating film; 19 is a P0 type half region for taking out the electrode of the p-type semiconductor well; 20 is a field insulating film formed by selectively oxidizing the surface portion of
is n''' for taking out the electrode of the n-type semiconductor well 16.
type semiconductor region, 21p and 21n are gate electrodes forming the electrodes of the MOS capacitor element, 22 is an insulating film between the eyebrows, 23 and 24 are contact holes for electrode extraction that can be formed in the interlayer insulating film 22 (not formed at the moment); 25 and 26 are contact holes for taking out the gate electrode.

According to the present master slice type semiconductor device, 92 capacitive elements C, C can be provided per cell without increasing the chip size.

That is, one is the gate electrode 21p and the p-type semiconductor well 15.
The other is a MOS capacitive element C formed between the gate electrode 21n and the n-semiconductor well 16, and one MOS capacitive element can form a basic MOS element. The signal delay for multiple inverters can be achieved using the following. There are three options for the two MOS capacitive elements: use only one of them, connect them in series to obtain different capacitance values, or use them individually. There are different ways to use it.

FIG. 6 shows one wiring example of the master slice type semiconductor device shown in FIGS. 4 and 5, and thereby a delay circuit as shown in FIG. 7 is obtained. FIG. 8 is a waveform diagram of the signals ■, ■, ■ of the delay circuit shown in FIG.

FIG. 9 shows an example of wiring in a conventional master slice type semiconductor device, that is, a master slice type semiconductor device without a MOS capacitive element, and this wiring example is similar to that shown in FIGS. In this case, since there is no capacitive element, inverters must be connected in cascade, resulting in the use of a large number of gates. It can be seen that the gate usage efficiency had to deteriorate significantly.As is clear from the comparison between FIG. 9 and FIG. 6, the master slice method with the MOS capacitive element shown in FIGS. 4 and 5 semiconductor devices have higher gate usage efficiency (
It is possible.

The embodiments shown in FIGS. 4 and 5 are twin tubes, but they are also applicable to those with an n-type semiconductor substrate/p-type semiconductor well structure, and those with a p-type semiconductor substrate/n-type semiconductor well structure. It goes without saying that the present invention can also be applied to objects.

(c, third embodiment) [Figures 10 to 13] 10th
11 and 11 show a third embodiment of the master slice type semiconductor device of the present invention, FIG. 10 is a plan view of a cell, and FIG. 11 is a sectional view taken along the line XI-XI in FIG. 10. It is.

This master slice type semiconductor device differs from the embodiments shown in FIGS. 1 and 2 and the embodiments shown in FIGS. 4 and 5 in that it is equipped with a switching transistor 5WTr, and The number of MOS transistors is eight. It has a capacitive element group that is electrically completely isolated from the semiconductor substrate, and FIG. 11 shows a cross-sectional structure of the capacitive element. In the figure, 27 is a semiconductor substrate, 28 is a p-type semiconductor well, 29 is a field insulating film,
30 is an electrode made of a first polycrystalline silicon layer formed on the field insulating film 29; 31 is, for example, a Si
, a dielectric film made of a film, 32 is an electrode made of a second polycrystalline silicon layer, and the electrode 32 and the dielectric film 31 are
A capacitive element C is constituted by the electrode 30.

33 is an insulating film, and 34 is a portion where a contact hole for taking out an electrode can be formed (the contact hole has not yet been formed at the stage of a master slice type semiconductor device).

In this embodiment, three capacitive elements having a capacitance ratio of 1:2:4 are provided for each cell, so that several types of capacitance values can be obtained by combining them. Various variations can be considered regarding the number of capacitive elements per cell and the capacitance ratio. The reason why the capacitive element is provided completely floating from the semiconductor substrate in this way is to allow digital circuits and analog circuits to be mounted together on the gate array. In other words, analog circuits require a large amount of capacitance and often require a coupling capacitor between circuits, but a coupling capacitor requires both electrodes to be electrically floating from the ground side. . Furthermore, if a MOS capacitive element is used as a substitute for a capacitor used in an analog circuit, one electrode becomes a pn junction and has bias dependence, which greatly hinders achieving the desired characteristics of the analog circuit. It is not preferable to use a MOS capacitive element even when it is not used as a ring capacitor. Therefore, both electrodes form a floating capacitive element.

Note that analog circuits often use switches in addition to capacitive elements, so a switching transistor was also provided.

FIG. 12 is a plan view showing one wiring example of the master slice type semiconductor device shown in FIGS. 10 and 11;
FIG. 3 is a circuit diagram showing a circuit (comparator) constituted by the wiring shown in FIG. 12. This comparator circuit is described in detail in Japanese Patent Application Laid-open No. 74318/1983.

Incidentally, the area for the substrate contact may be narrowed and the area of the capacitive element formation region may be increased accordingly, thereby increasing the number of capacitive elements per cell.

(H. Effects of the Invention) As is clear from the above description, the master slice type semiconductor device of the present invention is characterized by being provided with a delay adjustment capacitive element or a coupling capacitive element.

Therefore, according to the master slice type semiconductor device of the present invention, since there is a capacitive element for adjusting the delay amount or a capacitive element for coupling, many gates are allocated for delay,
Since there is no need to allocate a large number of gates for the coupling capacitor, the genit usage efficiency can be increased.

[Brief explanation of drawings]

1 to 3 are for explaining one embodiment of the master slice type semiconductor device of the present invention, in which FIG. 1 is a plan view showing the whole, FIG. 2 is a sectional view showing a capacitive element,
FIG. 3 is a plan view showing one wiring row, FIGS. 4 to 9 are for explaining a second embodiment of the master slice type semiconductor device of the present invention, and FIG. 4 is a plan view of a cell. figure,
5 is a cross-sectional view taken along line V-V in FIG. 4, FIG. 6 is a plan view showing one wiring example, FIG. 7 is a circuit diagram constructed by the wiring example shown in FIG. 6, and FIG. Figure 8 is a waveform diagram of each signal of the circuit shown in Figure 7, and Figure 9 is an attempt to obtain a circuit equivalent to the circuit obtained using the wiring example shown in Figure 6 using a conventional master slice type semiconductor device. FIGS. 10 to 13 are plan views showing wiring examples in this case, and are for explaining the third embodiment of the master slice type semiconductor device of the present invention. FIG. 10 is a plan view of a cell, and FIG. The figure is XI in Figure 10.
- A cross-sectional view taken along line XI, FIG. 12 is a plan view showing one wiring example, FIG. 13 is a circuit diagram showing a circuit obtained by the wiring example shown in FIG. 12, and FIGS. 14 and 15 are background 14 is a plan view of a master slice type semiconductor device, and FIG. 15 is a plan view of a cell. Explanation of symbols C... Capacitive element, 15.16... Semiconductor well, 2ip, 2in... Gate electrode. 3o, 32... Wiring layer, 31... Dielectric film. Floor plan Figure 1 C Existence! Cross-sectional diagram showing the pre-capacitance element Fig. 2 Fig. 3 Fig. 5 Circuit diagram Waveform diagram Fig. 7 Fig. 8 f3. . Plan view (F4 view technology) Figure 14 Figure 15

Claims (3)

[Claims] (1) A master slice type semiconductor device characterized by forming a MOS basic element and a delay adjustment capacitive element whose one electrode is connected to a power supply. (2) The master slice type semiconductor device according to claim (1), wherein the delay amount adjustment capacitive element is formed between the semiconductor well in which the MOS basic element is formed and the gate electrode. (3) The above M consists of a basic MOS element and two wiring layers laminated via a dielectric film.
A master slice type semiconductor device comprising: a coupling capacitive element for coupling between circuits constituted by basic OS elements; and a master slice type semiconductor device.