JPH02303068A - Semiconductor stacked structure and semiconductor device having same - Google Patents

Abstract

PURPOSE:To obtain a graded junction type heterojunction whose composition controllability and composition uniformity are improved by controlling the ratio of layer numbers of first semiconductor layers and second semiconductor layers, and changing a graded layer. CONSTITUTION:On a semi-insulative substrate 3 composed of Fe-doped InP, an undoped I-InP layer 4 and a graded layer are formed in order, and a buffer layer is formed. On the buffer layer, an S-doped N-In0.53Ga0.47As layer 11 is formed. This graded layer is formed by periodically laminating the undoped I-InP layers and the undoped I-In0.53Ga0.47As layers 11. By controlling the ratio of the number of the layers, the composition is changed. As to the N-In0.53Ga0.47 As layer 11 obtained in this manner, misfit dislocation is reduced, and surface state is excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a two-layer semiconductor structure having a heterojunction and a semiconductor device using the same.

(Prior art) Compound semiconductors and mixed crystal semiconductors have high electron mobility.
It has characteristics not found in single-element semiconductors such as Si and Ge, such as new physical phenomena caused by a unique energy band structure that has a light-emitting function.
It is attracting attention as a material for ultra-high-speed processing elements, ultra-high frequency transmitting elements, and optoelectronic elements.

In recent years, research and development has been particularly active on bipolar transistors and field effect transistors that utilize heterojunctions.

Semiconductor layers for manufacturing these semiconductor elements are usually formed by a molecular beam epitaxy method (hereinafter referred to as MBE method) or a metal organic vapor phase epitaxy method (hereinafter referred to as MOVPE method). When forming a heterojunction with these, Ga
Except for exceptional combinations such as As, AIAs, and AIGaAs, in which lattice matching is not necessary because the lattice constants are essentially the same, it is necessary to match the lattice constants to prevent the occurrence of misfit dislocations. For this purpose, InP and InGaAs, or GaAs and InGa
A combination of a binary compound semiconductor such as P and a ternary mixed crystal semiconductor, or a combination of a ternary mixed crystal semiconductor such as AlInAs and InGaAs and another ternary mixed crystal semiconductor is often used.

When the above-mentioned heterojunction interface is a tilted junction type, in order to gradually change the crystal composition while maintaining lattice matching,
A transition region (hereinafter referred to as graded layer) is formed. - As an example, Fig. 4 shows InP and 3 which is lattice matched to it.
A schematic diagram of a tilted junction type heterojunction in which Ino, 53Gao, and 47As, which are original mixed crystal semiconductors, are joined is shown. In FIG. 4, the InP layer 23 and In□, 53Ga□, 47A
A graded layer 24 made of In1-xGaxAsl-yPy is formed between the s-layers 25. In this graded layer 24, I
N and Ga, as well as P and As, coexist in the atomic plane of the V group element, and by controlling their atomic ratio, the composition is controlled and lattice matching is achieved. Actually MB
Forming a graded layer as described above by the E method or MOVPE method, in some cases, continuously while controlling the flux ratio of the molecular beam of the constituent elements, or the partial pressure ratio of the raw material gas containing the constituent elements. A method of changing is used.

(Problem to be solved by the invention) For example, binary compound semiconductors and ternary mixed crystal semiconductors, or
A graded layer formed when original mixed crystal semiconductors are made into a heterojunction is often a quaternary mixed crystal semiconductor. Therefore, in order to continuously change the crystal composition while maintaining lattice matching, it is necessary to strictly control the composition ratio of the three group III elements or two group III and V elements. This is one of the factors that makes it extremely difficult to control the composition ratio.

In addition, depending on the combination of semiconductor materials, the grown layer may undergo layer separation, resulting in a miscibility gap, or even if no clear layer separation occurs, microscopically non-uniform distribution or local composition may occur. different small groups (clusters)
may occur.

Naturally, such a raster causes a decrease in carrier transport efficiency, running characteristics, and lifetime, and has a negative effect on the electrical and optical properties of the crystal. Therefore, when used in semiconductor devices, this is one of the factors that degrades the static characteristics and high-speed/high-frequency characteristics of the device.
It is also one of the factors that reduces the uniformity of characteristics between semiconductor elements within a wafer.

An object of the present invention is to provide a tilted junction type heterojunction that solves these problems, reduces lattice misalignment, and improves composition controllability and composition uniformity, and a forming method for realizing the same. It's about doing.

(Means for Solving the Problem) A semiconductor stacked structure of the present invention has a semiconductor stacked structure having a heterojunction in which a first semiconductor layer and a second semiconductor layer are joined via a graded layer. The dead layer has a periodic stacked structure of the first semiconductor layer and the second semiconductor layer, and the period of the periodic stacked structure changes.

However, the first semiconductor layer and the second semiconductor layer may be made of a binary compound semiconductor or a ternary mixed crystal semiconductor.

Furthermore, a semiconductor element having at least a portion of the semiconductor stacked structure of the present invention has excellent electrical properties and optical properties, and variations in properties between elements can be reduced.

Further, a forming method for realizing such a semiconductor stacked structure of the present invention includes, for example, a first step of forming a predetermined number of second semiconductor layers on a first semiconductor layer, and a second step of forming a predetermined number of second semiconductor layers on a first semiconductor layer. a second step of forming a predetermined number of the first semiconductor layers on a semiconductor layer; and a first step of changing the ratio of the number of layers of the first semiconductor layer and the second semiconductor layer. and a third step of repeating the second step at least once.

(Function) In general, the basic physical properties of mixed crystal semiconductors formed by artificially stacking semiconductor layers on the order of atomic layers in an alternating manner are largely unknown, but they are not necessarily the same as those of conventionally structured mixed crystal semiconductors. I can't say that. However, since the fundamental physical properties of crystals are due to a wide range of periodic atomic arrangements, it is necessary to consider a relatively large volume containing many atoms, and therefore the carriers involved in this also have a certain degree of spread ( de Broglie wavelength). For example, the de Broglie wavelength of electrons involved in band edge absorption and light emission is several hundred angstroms at room temperature, and the number of atoms included in this wavelength is about 106. In other words,
Even if a crystal has a microscopically regular atomic arrangement, these are normally sufficiently averaged and reflected in the macroscopic fundamental physical properties.

FIG. 1 shows InP and Ino for detailed explanation of the present invention.
A schematic diagram of a tilted heterojunction in which , 5Gao, and 5As are joined is shown. Compared to the conventional method shown in Figure 4, In
An important difference is that the graded layer made of 1-xGaxAsl- and Py is formed by a laminated structure of an InP layer 1 and an In□, 53Gao, and 47As layer 2. In addition, only one type of atom of P or As exists in the atomic plane of group V elements, while III
Another point that differs from the conventional structure is that the atomic surfaces of the group elements include surfaces with only In atoms and surfaces with In and Ga atoms mixed in a certain ratio (0.53:0.47). be.

In Fig. 1, the crystal composition is controlled by InP layer 1 and InP layer 1.
, 53Gao, and 47As layers 2, and by gradually changing the ratio, a graded layer with a composition changed from InP to Ino, 53Ga□, and 47As is formed. There is. In other words,
In the conventional method, it is necessary to directly control the ratio of the number of atoms of In, Ga, As, and P (i.e., control the four elements), whereas according to the method of the present invention, the ratio of the number of atoms of In, Ga, As, and P must be controlled directly,
It is only necessary to control the number of layers (ie, two elements) of the no, 53Gag, and 47As layers.

In Figure 1, in order to have the properties of a conventional heterojunction that corresponds to a sufficiently averaged composition,
It is necessary to make the thickness of the semiconductor layer serving as a structural unit sufficiently smaller than the de Broglie wavelength described above. This condition can be fully satisfied by setting the number of layers to several. Therefore, for example, InF3 layer, In□, 53Gao, 4
By alternately stacking two 7As layers, In0.81G
a0.19AS0.4P0.6, also InF3 layer, I
It is possible to form a quaternary mixed crystal semiconductor layer having a composition corresponding to In0.62Ga0.38AS0.8P0.2 by alternately stacking four layers of n□, 53Ga□, and 47As.

Figure 5 shows In1-E GaxAs1 which is lattice matched to InP.
-, is a diagram showing the crystal composition of a Py quaternary mixed crystal semiconductor. The present invention will be explained using FIG. In FIG. 5, InP corresponds to point P, and Ino, 53Ga□, and 47As correspond to point Q. Then, the InP layer and In0.53Ga□,
47As layers are alternately stacked, and the ratio of the number of layers is a□:
With a crystal having b□, it is possible to realize an In1-, GaxAsl-yPy quaternary mixed crystal semiconductor corresponding to the composition at the R point. Therefore, by gradually changing the layer number ratio ao:bo, a mixed crystal with an arbitrary composition on the solid line in the figure can be realized, and from InP to InP along the solid line (that is, while always maintaining lattice matching to InP). Ino, 53Ga□, 4
A graded junction type heterojunction with a composition changed to 7As can be formed.

In this way, if the method of the present invention is used, semiconductor layers that are originally lattice matched (InP and InO, 53G
Since a Peter junction is formed by laminating layers of aO, 47AS), lattice misalignment does not occur in the graded layer. This greatly facilitates control of the crystal composition in the graded layer. Further, as described above, the fact that the number of elements to be controlled is small, such as the number of each semiconductor layer, is also one of the factors that facilitates composition control. Furthermore, always In
Since it is sufficient to form a semiconductor layer made of either P, In□, 53Ga□, or 47As, the occurrence of a miscibility gap can be suppressed, and as a result, the composition uniformity is improved.

Although FIG. 1 describes a beterojunction in which InP and InGaAs are joined, the invention is not limited to this, and
A combination of As and other binary compound semiconductors such as InGaP and ternary mixed crystal semiconductors, or InAlAs and InGaP
The effects of the present invention can also be obtained in combinations of ternary mixed crystal semiconductors such as As. Also, GaAs, AlAs and A
It is applicable not only to the combination of lGaAs but also to the combination of binary compound semiconductors.

(Example) Next, the present invention will be explained using the drawings.

FIG. 2 is a sectional view of a grown crystal for explaining the first embodiment of the present invention, and shows a case where the present invention is applied to a buffer layer.

In FIG. 2, an undoped 1-InP layer 4 of 3000 layers and a graded layer of about 400 OA are sequentially formed on a semi-insulating substrate 3 made of Fe-doped InP to form a buffer layer. On this buffer layer, an additional 50
00 S-doped n-In□, 53Gag, 47A complex 1
1 is formed. The plane orientation of the substrate is (111)
Side B was used. Graded layer is undoped 1-InP
It is formed by periodic stacking of undoped 1-Ino, 53Gao, and 47As layers, and the composition is changed in six stages by controlling the ratio of the number of these layers. The layer structure of this graded layer is shown below.

(Left below) In this case, for example, 1-Ino, aIGao, 19Aso
, 4Po, s layer 7 is InF 3 layer-Ino, 53Ga□
, 47As two layers were laminated as one structural unit, and 40 of these structural units were laminated.

Each semiconductor layer constituting the graded layer was formed at a substrate temperature of 375° C. by atomic layer epitaxy (hereinafter referred to as ALE method) using a hydride vapor phase growth apparatus. Regarding this method, for example, A. Usui et al.
Usui et al.), Japanese Journal of Applied Physics (Japanese Journal of Applied Physics)
se Journal of Applied Phys.
ics), volume 25, 1986, page L212. In addition, 1-InP layer 4 and n-In□, 53G
a□, 47As layer 1 was grown at a substrate temperature of 6 using the usual hydride vapor phase epitaxy method (hereinafter referred to as hydride VPE method).
Formed at 00°C.

n-In□, 53Ga□, 47As obtained above
Layer 11 had fewer misfit dislocations and a better surface condition than that obtained by the conventional method.

FIG. 3 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention, and shows a case where the present invention is applied to the formation of a pn junction.

In FIG. 3, a buffer layer 13 having a layer structure similar to that shown in the first embodiment is formed on a semi-insulating substrate 12 made of Fe-doped InP. On this buffer layer 13, 5000 Zn-doped p-In□, 53G
a□, a 47As layer 14, a graded layer of approximately 680 layers, and an S-doped n-InP layer 22 of 5000 layers are formed in sequence, including 1-Ino, 7sGao, 24Aso, 5P.
One layer of approximately 70 undoped spacers consisting of o, s 18
A pn junction is formed by a heterojunction consisting of an n shadow region with a wide forbidden band width and a p shadow region with a narrow forbidden band width. In addition, p-In□, 53Gao, 47Asi
14 and the n-InP layer 22 were formed by the hydride VPE method, and the graded layer was formed by the ALE method.

Also, the carrier densities of the n shadow region and the p shadow region are n=3X1017cm-3 and p=7X1018c, respectively.
m = closed.

The layer structure of the graded layer is shown below.

After etching the p-n junction obtained above into a predetermined pattern, AuZn was added on the surface of the p-In0.530a0.47A8 layer 14 and the surface of the n-InP layer 22, respectively.
When we formed ohmic electrodes made of Ni and AuGeNi and fabricated a large number of pn junction diodes on a 2-inch wafer and evaluated them, we found that the current-voltage characteristics were significantly lower than those using pn junctions obtained by conventional methods. Improved uniformity and reverse pressure resistance.

In addition, in the above embodiment, the case where a (111)B substrate was used was described, but the present invention is not limited to this.
It is also possible to use a substrate having other plane orientations, including (100) planes or planes tilted several degrees from these planes.

Furthermore, the constituent units used to form the semiconductor layer of each composition are not limited to those shown in the above embodiments, and are, for example, InO, 8
When forming a 1Ga0.19AS0.4P0.6 layer,
InF3 layer-In. , 53Ga□, 47As single layer-In
P1 layer-In□, 53Gao, 47AS1 layer-InP1
The structural units may be formed using other laminated structures such as layers, and similarly, the semiconductor layers of each composition are not limited to the laminated structures shown in the above examples, but may be formed using other laminated structures. .

Further, in the above embodiment, the present invention is applied to InP and InG.
Although the case where it is applied to the formation of an aAs heterojunction has been described, the present invention is not limited thereto, and can be applied to a heterojunction in which other binary compound semiconductors or ternary mixed crystal semiconductors are joined. As stated before.

Furthermore, in the above embodiments, the present invention was used to form a buffer layer and a pn junction, but
It goes without saying that the present invention is not limited to this, and can also be applied to other semiconductor crystals or semiconductor elements such as heterobipolar transistors and field effect transistors.

(Effects of the Invention) As explained above, according to the present invention, composition control for achieving lattice matching becomes extremely easy, and as a result, lattice misalignment is reduced and composition uniformity is improved in a tilted junction. This has the effect of easily realizing type heterojunction. Therefore, this greatly contributes to improving the characteristics of various semiconductor crystals and semiconductor devices using heterojunctions.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a semiconductor crystal for explaining the semiconductor laminated structure of the present invention, and FIG.
FIG. 3 is a cross-sectional view of a semiconductor crystal of a second embodiment for explaining the present invention, and FIG. 4 is a cross-sectional view of a semiconductor crystal for explaining a conventional heterojunction. A cross-sectional view, FIG. 5 shows In14GazAs lattice matched to InP.
FIG. 1 is a diagram showing the composition of 1P.

1, 23 InP layer, 2.25=Ing, 53Gag,
47A4.3, 12... Semi-insulating substrate (InP), 4
．． 5.1-InP layer, 6°°-1-In□, gIGa□
, □gAsO, 2P□, B layer turtle 7°=i-Ino, 5t
Gao, x9Aso, 4Po, a-layer 110.1-Ino
, 53Gao, 47As layer, 1l-n-In□, 53G
ao, 47As layer, 13-... buffer layer (i-InP
Layer 1-In1-xGaxAsl-, P, :xO-+0
．． 47.

y:1→O), 14.15...p-In□, 53Ga
o, 47As layer, 19=n-In□, BIGa□, 1g
As□, 4PO16 layer 120=n-In□1g1Ga□
, ggAs□, 2P□, 8JiiiF, 21.22=n
-InP layer, 24... graded layer (Inl-xG
axAsl-, P, : x:0-+0.47゜Y:1
→0)

Claims (3)

[Claims] (1) In a semiconductor stacked structure having a heterojunction in which a first semiconductor layer and a second semiconductor layer are in contact with each other via a graded layer, the graded layer is connected to the first semiconductor layer and the second semiconductor layer. 1. A semiconductor laminated structure having a periodic laminated structure with layers and a period of the periodic laminated structure changing. (2) The semiconductor stacked structure according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are made of a binary compound semiconductor or a ternary mixed crystal semiconductor. (3) A semiconductor device characterized in that at least a portion thereof has a semiconductor stacked structure according to claim 1 or 2.