JPH0229535U - - Google Patents
Info
- Publication number
- JPH0229535U JPH0229535U JP1988108171U JP10817188U JPH0229535U JP H0229535 U JPH0229535 U JP H0229535U JP 1988108171 U JP1988108171 U JP 1988108171U JP 10817188 U JP10817188 U JP 10817188U JP H0229535 U JPH0229535 U JP H0229535U
- Authority
- JP
- Japan
- Prior art keywords
- attached
- lead plate
- substrate part
- power chip
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図及び第２図は本考案の第１の実施例を示
すもので、第１図は平面図、第２図は第１図の
―線に沿う断面図であり、第３図及び第４図は
本考案の第２の実施例を示すもので、第３図は斜
視図、第４図は第３図の―線に沿う断面図で
ある。
図面中、１は基板（基板部）、２はリードプレ
ート、４は端子プレート、６はヒートシンク部、
７はパワートランジスタ（パワーチツプ）、１３
はヒートシンク部、１４はケース（基板部）であ
る。
1 and 2 show a first embodiment of the present invention, in which FIG. 1 is a plan view, FIG. 2 is a sectional view taken along the line - in FIG. 1, and FIGS. FIG. 4 shows a second embodiment of the present invention, FIG. 3 is a perspective view, and FIG. 4 is a sectional view taken along the line -- in FIG. In the drawing, 1 is a board (substrate part), 2 is a lead plate, 4 is a terminal plate, 6 is a heat sink part,
7 is a power transistor (power chip), 13
1 is a heat sink portion, and 14 is a case (board portion).
Claims (1)
記基板部に付設された回路素子を該リードプレー
トに接続するものにおいて、前記リードプレート
に一体的に形成されたヒートシンク部と、このヒ
ートシンク部に高温半田等で密着状態に付設され
たパワーチツプとを具備してなるパワーチツプ一
体型集積回路。 A metal lead plate is attached to a substrate part, and a circuit element attached to the substrate part is connected to the lead plate. A power chip-integrated integrated circuit comprising a power chip attached in close contact with solder or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988108171U JPH0229535U (en) | 1988-08-16 | 1988-08-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988108171U JPH0229535U (en) | 1988-08-16 | 1988-08-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0229535U true JPH0229535U (en) | 1990-02-26 |
Family
ID=31343252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988108171U Pending JPH0229535U (en) | 1988-08-16 | 1988-08-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0229535U (en) |
-
1988
- 1988-08-16 JP JP1988108171U patent/JPH0229535U/ja active Pending
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