JPH0229461Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an analog multiplication circuit that multiplies two input signals in an analog manner and outputs the result.

[Conventional technology]

Various types of multiplier circuits that multiply two input signals in an analog manner have been developed in the past.For example, one input signal is a DC control voltage, the other is an AC signal, and a voltage controlled amplifier (VCA) is used. It is used in a variety of ways, such as as an FM multiplex circuit where one of the input signals is an FM composite signal and the other is a subcarrier signal. In this case, the characteristics required of this type of multiplier circuit are a high signal-to-noise ratio and a wide dynamic range of the input signal, and in recent years, this type of circuit is often made into an IC (integrated circuit). Therefore, the structure is more suitable for IC implementation. However, there is no conventional multiplication circuit that satisfies all of the above characteristics, and the development of one has been desired.

[Problem that the invention attempts to solve]

This idea was made in view of the above-mentioned circumstances, and has a high SN ratio and a wide input dynamic range.
Furthermore, the purpose is to provide an analog multiplier circuit that is extremely suitable for IC implementation.

[Means for solving problems]

In order to achieve the above object, the analog multiplier circuit of this invention has a first differential transistor pair to which a first signal is input, and a power line between both collectors of the first differential transistor pair and a power supply line. a second differential transistor pair to which a second signal is input; a third differential transistor pair and a fourth differential transistor pair whose emitters are each commonly connected via a forward-direction diode; and a current mirror circuit, each of which operates in a common base type, and whose bases are commonly connected, and a collector of one transistor of the first differential transistor pair is connected to the first differential transistor pair. 3. Connect the base of each transistor of the fourth differential transistor pair to the base of each other transistor of the first differential transistor pair, and connect the collector of the other transistor of the first differential transistor pair to the base of each other transistor of the third and fourth differential transistor pairs. , and the collectors of both transistors of the second differential transistor pair are connected to the common connection points of the diodes connected to the respective emitters of the third and fourth differential transistor pairs, and , the collector of one transistor of the third transistor pair and the collector of the other transistor of the fourth transistor pair are commonly connected, and the signal obtained at the common collector is supplied to the emitter of one transistor of the output side transistor pair. and the collector of the other transistor of the third transistor pair and the collector of one transistor of the fourth transistor pair are commonly connected, and the common collector is supplied to the emitter of the other transistor of the output side transistor pair. , further, each collector of one transistor and the other transistor of the output transistor pair are connected to the input side and the output side of the current mirror circuit, respectively, so that an output signal is obtained from the output side of the current mirror circuit. be.

[Effect]

According to this invention, each collector current change of the first differential transistor pair corresponds to the first signal, and this current change is further applied to the second, third, and fourth transistors.
A portion consisting of a differential transistor pair performs current proportional multiplication according to the second signal, and this current proportional multiplication output corresponds to the multiplication of the first signal and second signal in a portion consisting of an output side transistor pair and a current mirror circuit. This output is taken out as an output, and this output has a high S/N and a wide dynamic range, and can be easily integrated into an IC in terms of circuit configuration.

〔Example〕

Hereinafter, embodiments of this invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of this invention. In the figure, 1 is the transistor Q
1, Q2 is a differential transistor pair,
An input signal (first signal) vx is supplied to the base of the transistor Q1, and the base of the transistor Q2 is grounded. The collector of the transistor Q1 is diode-connected transistors (hereinafter simply referred to as diodes) D3, D2, and D1.
It is connected to the positive power supply terminal 8 via. In this case, the directions of the diodes D1 to D3 are in the forward direction as shown in the figure. Similarly, the collector of the transistor Q2 is connected to the forward diode D6,
It is connected to the positive power supply terminal 8 via D5 and D4. In this case, the diode forward voltage drop is approximately
Since the voltage is 0.6V, the collector potential of transistors Q1 and Q2 is as follows, assuming that the positive power supply voltage is V _CC .
(V _CC −1.2V). And transistor Q
The emitters of 1 and Q2 are transistors Q11 and Q
12, and the emitters of transistors Q11 and Q12 are connected to resistors 15 and 1, respectively.
6 (both values are R) to the negative power supply terminal 10. Further, diodes D15, D16, D17, and D18 are inserted in series between the positive power supply terminal 8 and the negative power supply terminal 9, and the diodes D16 and D1
Further, a constant current circuit 7 is interposed between the circuit 7 and the circuit 7. As a result, the potential on the cathode side of diode D16 is fixed at (V _CC -1.2V), and the potential on the anode side of diode D17 is set to -1.2V.
If V _EE is used, it is fixed at (-V _EE +1.2V). The bases of the transistors Q11 and Q12 described above are connected to the anode of the diode D17, and as a result, the transistors Q11 and Q1
2 serves as a constant current source. In this case, since the voltage drop between the base and emitter of transistors Q11 and Q12 is 0.6V, the voltages applied across the resistors 15 and 16 are both 1.2-0.6=0.6V,
Therefore, the values of the currents flowing through the resistors 15 and 16 are equal, I ₀ =0.6/R. In this way, transistors Q11 and Q12 each function as a constant current source with a current value I ₀ .

Next, 3 is a differential transistor pair consisting of transistors Q5 and Q6, with diodes D7 and D8 connected in series in the forward direction to the emitter of the transistor Q5, and diodes D9 and D10 connected in the forward direction to the emitter of the transistor Q6. connected in series. And these diodes D8 and D10
By connecting the cathodes of transistors Q5 and Q6, the emitters of transistors Q5 and Q6 are commonly connected through diodes D7 and D8 and D9 and D10. 4 is a differential transistor pair configured similarly to differential transistor pair 3;
The emitters of transistors Q8 and Q7 are commonly connected via diodes D11 and D12 and D13 and D14, respectively. Further, the bases of transistors Q5 and Q7 are commonly connected and then connected to the collector of transistor Q1, and the bases of transistors Q6 and Q8 are connected to the collector of transistor Q2.

Next, 2 is a differential transistor pair consisting of transistors Q3 and Q4, and the input signal vy (second signal) is supplied to the base of the transistor Q3, and the base of the transistor Q4 is grounded. The emitter of transistor Q3 is connected to one end of resistor 11 and the collector of transistor Q13, the emitter of transistor Q4 is connected to the other end of resistor 11 and the collector of transistor Q14, and the collectors of transistors Q3 and Q4 are connected to each other. , a common cathode of diodes D8 and D10, and a common cathode of diodes D12 and D14, respectively. Transistor Q1
3 and Q14 are the aforementioned transistors Q1, respectively.
1, Q12, the base is connected to the anode of the diode D17, and each emitter is connected to the resistor 17, 1.
8 (both values are R) to the negative power supply terminal 9. Therefore, transistors Q13, Q1
4 are constant current sources each having a current value I ₀ .

Next, transistors Q9 and Q10 are a pair of transistors whose common bases are connected to the cathode of diode D16, and whose emitters are connected to the positive power supply terminal 8 through resistors 12 and 13 (both values are R/2), respectively. It is connected to the. In this case, considering the voltage drop between the emitters and bases of transistors Q9 and Q10, there is always a voltage drop across each of resistors 12 and 13.
A voltage of 0.6V is applied, and as a result, the resistance 12,1
3, a constant current of value 2I ₀ flows through each of them. The emitters of transistors Q9 and Q10 are connected to the collectors of transistors Q31 and Q32,
The emitter of transistor Q31 is transistor Q
The emitter of the transistor 32 is connected to the collectors of the transistors Q6 and Q7. Also, transistor Q
31 and Q32 are commonly connected and then connected to the cathode of diode D16.

Next, 6 is a current mirror circuit consisting of a diode D20 and a transistor Q15 whose base is connected to the anode of this diode D20, and a transistor Q9 is connected to the anode of the diode D20 (input side of the current mirror circuit 6). The collector is connected to the collector of transistor Q15, the collector of transistor Q10, and the output terminal.
Tout is connected. Also, diode D2
A resistor 19 is interposed between the cathode of the transistor Q15 and the negative power supply end 9, and a resistor 20 is interposed between the emitter of the transistor Q15 and the negative power supply end 9. In the above configuration, as can be seen from the figure, the collector current
The sum of I _A and I ₉ is 2I ₀ , and the collector current I _B
The sum of I ₁₀ is 2I ₀ . Furthermore, R _L shown in the figure is a load resistance.

Next, the operation of this embodiment with the above-described configuration will be explained.

First, the direction and magnitude of the current ix flowing through the resistor 10 inserted between the emitters of transistors Q1 and Q2 change depending on the input signal vx. The direction and magnitude of the current iy flowing through the inserted resistor 11 change depending on the input signal vy.

The circuit described above is based on the basic principle of so-called current proportional multiplication, and the current I ₁ to
The following relationship holds true for I ₆ .

I ₄ /I ₃ = I ₁ /I ₂ ...(1) I ₆ /I ₅ = I ₂ /I ₁ ...(2) In addition, transistors Q11 to Q14 each function as a constant current source with a current value I ₀ . Therefore, I ₁ + I ₂ = 2I ₀ ……(3) I ₂ −I ₁ = ix ……(4) I ₃ + I ₄ + I ₅ + I ₆ = 2I ₀ ……(5) (I ₅ + I ₆ ) - (I ₃ + I ₄ ) = iy ...(6) The following relationship holds, and further, from the figure, I _A = I ₃ + I ₅ ... (7) I _B = I ₄ + I ₆ ... (8) I can understand that there is a relationship. Then, when formulas (1) to (8) above are rearranged, transistor Q3
1. The collector currents I _A and I _B of Q32 are the currents, respectively.
The value corresponds to the product of ix and iy, and is shown in the following equation.

I _A = I ₀ + k (ix·iy) ... (9) I _B = I ₀ - k (ix * iy) ... (10) Note that k is a constant and I ₀ is a DC bias value.

Then, the collector currents I ₉ and I ₁₀ are respectively I ₉ = 2I ₀ − I _A ……(11) I ₁₀ = 2I ₀ − I _B ……(12), and the above equations (11) and (12) are Substituting equations (9) and (10), the collector currents I ₉ and I ₁₀ are respectively I ₉ = I ₀ − k (ix・iy) ... (13) I ₁₀ = I ₀ + k (ix・iy) ...(14) Then, the collector current I ₉ is supplied to the input side (control side) of the current mirror circuit 6, and the collector current I ₁₀ is supplied to the output side of the current mirror circuit 6 and the load resistance R _L. . As a result, a current corresponding to the difference between the collector currents _I9 and _I10 , that is, a current of 2ix·iy flows through the load resistor R _L. Therefore, the output voltage Vout becomes a signal proportional to the product of the input signals vx and vy (the proportionality constant is 2). In the above description, when the currents ix and iy each flow toward the left arrow side in the drawing, their signs are assumed to be positive.

Now, if we consider the maximum allowable value of the input signal vx, the forward voltage drop due to the diodes D1 to D3 is always approximately 1.8, regardless of the magnitude of the current _I1 .
(0.6×3)V, the maximum allowable value of the input signal vx is V _CC −1.8V. On the other hand, if a low resistance is used for the collector load of the transistor Q1, the voltage drop across this resistance changes depending on the current _I1 , so it is impossible to obtain a large tolerance value as described above. . In this embodiment, the allowable value of the input signal is large as described above, but the allowable value of the output signal is also large. In other words, the multiplication result currents I _A and I _B are the output side transistor pair Q
Determine the collector current of transistor pair Q9, Q10, and further determine the collector current of transistor pair Q9, Q1.
A current is calculated on the output side by a current mirror circuit 6 provided corresponding to 0. in this case,
The voltage across the load resistor R _L can be varied over almost the entire range of the power supply voltage, increasing the efficiency of use of the power supply voltage. The above-mentioned effects are combined to provide an extremely wide dynamic range as a whole.

Further, since forward direction diodes D7 to D14 are appropriately connected to the emitters of the differential transistor pairs 3 and 4 constituting the multiplier, the emitter resistance of the differential transistor pairs 3 and 4 increases. , the signal-to-noise ratio is extremely high.

Furthermore, since the collectors of the differential transistor pairs 3 and 4 are connected to the positive power supply end 8 via the diodes D15 and D16 and the base and emitter of the transistor Q31 or Q32, the potential thereof is approximately V _CC -1.8. It is clamped to V, making the operation extremely stable.

Moreover, according to this configuration, most of the active elements used in the circuit are NPN transistors, so it can be seen that it is extremely suitable for IC implementation.

Next, FIG. 2 is a circuit diagram showing the configuration of a modification of the circuit shown in FIG. 1.

Most of the configuration and operation of this modification are the same as those of the previous embodiment, so they will not be explained in detail here, but the difference is that the number of diodes is changed to change the circuit operating point and clamp voltage. Furthermore, how to handle the output after current proportional multiplication is to connect the collectors of transistors Q5 and Q8 and the collectors of transistors Q6 and Q7 directly to the emitters of transistors Q9 and Q10 (output side transistor pair), respectively. Transistors Q20 and Q2 are configured to supply constant current to each emitter of transistors Q9 and Q10.
The point is that a constant current circuit consisting of 1 is used.

As is clear from the above description, the number of diodes in each part is not limited to the number shown in FIGS. 1 and 2, but may be any number as long as predetermined bias conditions etc. are satisfied.

[Effect of idea]

As explained above, according to this invention, the first
a first differential transistor pair into which a signal is input;
A diode is inserted in the forward direction between both collectors of the first differential transistor pair and the power supply line, a second differential transistor pair to which the second signal is input, and a diode whose emitter is inserted in the forward direction. A third differential transistor pair and a fourth differential transistor pair that are commonly connected through the transistor, output side transistors that operate in a common base format and whose bases are commonly connected, and a current mirror circuit are provided. The collector of one transistor of the first differential transistor pair is connected to the base of each transistor of the third and fourth differential transistor pairs, and the collector of the other transistor of the first differential transistor pair is a collector connected to the base of each other transistor of the third and fourth differential transistor pair;
The collectors of both transistors of the differential transistor pair are connected to the common connection points of the diodes connected to the emitter sides of the third and fourth differential transistor pairs, and the collector of the transistor and the fourth
The collectors of the other transistor of the transistor pair are connected in common, and the signal obtained at the common collector is supplied to the emitter of one transistor of the output transistor pair, and the collector of the other transistor of the third transistor pair and the third transistor of the third transistor pair are connected in common. The collectors of one of the transistors of the four-transistor pair are connected in common, and the common collector is supplied to the emitter of the other transistor of the output transistor pair, and each of the transistors of one and the other transistor of the output transistor pair is supplied to the common collector. Since the collector is connected to the input side and the output side of the current mirror circuit, and the output signal is obtained from the output side of the current mirror circuit,
The emitter resistance increases and the S/N ratio becomes extremely high.
Moreover, it is possible to obtain the effect of wide input/output dynamic range. In addition, since the circuit can be constructed using the same type of active elements, IC
This provides advantages that are extremely suitable for

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the structure of an embodiment of this invention, and FIG. 2 is a circuit diagram showing the structure of a modified example of the same embodiment. 1... Differential transistor pair (first differential transistor pair), 2... Differential transistor pair (second differential transistor pair), 3... Differential transistor pair (third differential transistor pair), 4... …
Differential transistor pair (fourth differential transistor pair), 5... transistor pair (output side transistor pair), 6... current mirror circuit.

Claims (1)

[Claims for Utility Model Registration] A first differential transistor pair to which a first signal is input; diodes each inserted in the forward direction between both collectors of the first differential transistor pair and a power supply line; A second differential transistor pair to which the second signal is input, and a third differential transistor pair and a fourth differential transistor pair whose emitters are commonly connected through forward diodes, each operating in a base-grounded format. and a current mirror circuit and an output side transistor whose bases are commonly connected, and a collector of one transistor of the first differential transistor pair is connected to the third and fourth differential transistor pairs. the collector of the other transistor of the first differential transistor pair is connected to the base of each other transistor of the third and fourth differential transistor pairs; The collectors of both transistors of the two differential transistor pairs are connected to the common connection points of the diodes connected to the emitter sides of the third and fourth differential transistor pairs, and
A collector of one transistor of the third transistor pair and a collector of the other transistor of the fourth transistor pair are commonly connected, and a signal obtained at the common collector is supplied to an emitter of one transistor of the output transistor pair. , the collector of the other transistor of the third transistor pair and the collector of one transistor of the fourth transistor pair are commonly connected, and the common collector is supplied to the emitter of the other transistor of the output side transistor pair;
Furthermore, each collector of one transistor and the other transistor of the output transistor pair are connected to the input side and the output side of the current mirror circuit, respectively, and an output signal is obtained from the output side of the current mirror circuit. Multiplication circuit.