JPH02291037A - Memory device - Google Patents

Abstract

PURPOSE:To shorten a memory clear time by providing a high-speed memory clear circuit in a memory control part. CONSTITUTION:When it is desired to clear the contents of a memory 2, a memory clear signal is inputted to a memory control part 1. When the memory clear signal is inputted, the memory control part 1 activates a high-speed memory clear circuit 3 and the high-speed memory clear circuit 3 clears the contents of the memory 2 by using the address / data bus of the memory 2. At such a time, the high-speed memory clear circuit 3 makes all memory blocks 21-24 effective. Accordingly, low-order address bytes inputted form signal lines 121 and 122 to the memory blocks 21-24 are simultaneously increased or decreased and 0 or 1 is written to the memory 2. Then, the contents of all the memory blocks 21-24 are simultaneously cleared in the respective memory blocks 21-24.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory device, and particularly to a memory device using random access memory (hereinafter referred to as RAM).

(Prior Art) In the past, readable/writable RAMs have been widely used as internal memories in general K1 computer systems and the like. These memories are controlled by addresses, the lower byte of which is used as the physical address of the memory, and the upper byte used to control each memory block.

Next, an example of a conventional memory device will be described with reference to the drawings.

FIG. 8 is a block diagram showing an example of the configuration of a general memory device, and FIG. 4 is an explanatory diagram showing a memory clearing method thereof.

In FIG. 8, 1 is a memory control unit, 2 is a memory, and 21
~24 are the first to fourth memory blocks, 111 respectively.
, 112 are signal lines for upper memory address bytes, 121 and 122 are signal lines for lower memory address bytes, and 113 and 114 are memory read signal lines and memory write signal lines, respectively.

As a result, the lower byte of the memory address is used as a physical address for memory 2K, and the upper byte is used for control to access the memory 2 by combination K with the memory read/write signal.

As shown in Figure 4, when attempting to clear the memory space, all memory addresses are incremented and each address is
is written. Therefore, only the address of memory 2 is
You need to clear all addresses one by one.

(Problem to be Solved by the Invention) In the conventional memory device described above, when clearing the memory contents, it is necessary to access all memory addresses and perform an O write, so there is a drawback that the memory clearing time becomes long. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device configured to eliminate the above-mentioned drawbacks and shorten the memory clear time by providing a high-speed memory clear circuit in a memory control section.

(Means for Solving the Problems) A memory device according to the present invention includes a memory consisting of a plurality of memory blocks for storing data using lower memory addresses, and a memory control unit for controlling the memory using upper memory addresses. This is a book consisting of.

The memory device is configured such that a memory clear signal enables all of the plurality of memory blocks, ignoring the upper addresses, and allows the plurality of memory blocks to be cleared at the same time.

(Implementation row) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory device according to the present invention, and FIG. 2 is an explanatory diagram showing a memory clearing method according to the present invention.

In FIG. 1K, similar elements to those in FIG. 2 are numbered similarly. In addition, 3 is a high-speed memory clear circuit, 115
1 is a memory clear signal line, and 11B is a memory clear lower address byte signal line.

When it is desired to clear the contents of the memory 2, a memory clear signal is input to the memory control section 1. When the memory clear signal is input, the memory control section 1 activates the high speed memory clear circuit 3. The high speed memory clear circuit 3 uses the address/data path of the memory 3 to clear the memory contents.

At this time, the high-speed memory clear circuit 3 ignores the upper address byte conventionally used for controlling the memory blocks 21-24, and clears all the memory blocks 21-2.
4 is valid (accessible state).

Therefore, the lower address bytes inputted to the memory blocks 21 to 24 from the signal lines 121 and 122 are simultaneously incremented or decremented, and the memory 2 stores %Ql or 1
1N is written. Therefore, each memory block 21 to 2
4, as shown in FIG.
The contents of 4 are cleared at the same time. At this time, addresses may be counted up to the maximum address value of the address bus.

(Effects of the Invention) As explained above, the present invention provides a high-speed memory clear circuit in the memory control unit, which eliminates the need to clear memory contents by accessing all memory addresses in conventional memory devices. Since only the maximum memory address of the memory blocks 21 to 24 needs to be accessed, the memory clearing time can be significantly reduced.

The above is more effective as the memory has a larger capacity and the number of memory blocks is larger, and furthermore, the larger the number of memory banks is, the more effective it is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory device according to the present invention, and FIG. 2 is an explanatory diagram showing a memory clearing method thereof. FIG. 8 is a block diagram showing an example of a memory device according to the prior art, and FIG. 4 is an explanatory diagram showing a memory clearing method thereof. 1...Memory control unit 2@●●Memory 21 to 24●●●Memory block 3...High speed memory clear circuit

Claims (1)

[Claims] A memory device comprising a memory consisting of a plurality of memory blocks for storing data according to a lower memory address, and a memory control section for controlling the memory according to an upper memory address, the memory device being configured to be operated by a memory clear signal. A memory device characterized in that the memory device is configured to enable all of the plurality of memory blocks ignoring the upper address and to clear the plurality of memory blocks at the same time.