JPH02290069A - Large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To shorten a delay time in the case of the high-speed operation of a large-scale integrated circuit and the like by a method wherein when the bipolar CMOS internal cell of a gate array LSI of a master slice system is constituted, a circuit, which is formed by connecting in parallel an arbitrarily desired number of pieces of MOS Trs for driving the bipolar transistor(Tr) of the output stage of functional blocks, is constituted. CONSTITUTION:The arrangement of functional blocks on a chip cell of a large- scale integrated circuit constituting an inverter and a wiring are decided and thereafter, in the case the load capacity of a corresponding block is small, a P-channel MOS Tr 7 is connected between a base of an N-P-N Tr 5 and a power terminal 13. Moreover, an N-channel MOS Tr 10 is connected between a Tr 6 and an output terminal 15 for driving the Tr 6. In this state, in the case a delay time is increased on the ground that the load capacity of the relevant block is large, a P-channel MOS Tr 8 is connected with the Tr 7 in parallel to the Tr 7 and an N-channel MOS Tr 11 is connected with the Tr 10 in parallel to the Tr 10. The ON-resistance of each drive Tr of the Trs 5 and 6 is reduced and even in the case the load capacity is large, the high-speed operation of the large-scale integrated circuit is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type large-scale integrated circuit, and more particularly to a large-scale integrated circuit capable of configuring a Bi-CMOS type internal cell.

[Conventional technology]

Various master slices have been designed in the past in order to shorten the design period of large-scale integrated circuits (hereinafter referred to as LSI).
It is used. The conventional master slice type LSI technology will be explained using a gate array as an example.

FIG. 6 is a plan view showing an example of a conventional gate array LSI.

The LSI chip 37 has a bonding pad 4 and an input/output circuit area 3 on its outer periphery, and has an internal cell area 2 in which internal cells are repeatedly arranged in the X direction.

The conventional mask slice method gate array LS described above
In I, when configuring the desired logic using the B i-CMOS type internal cells, only the functional blocks prepared in advance were used.

[Problem to be solved by the invention]

In the conventional large-scale integrated circuit described above, when constructing a Bi-CMOS type internal cell, only functional blocks prepared in advance are used, so the delay time increases as the load capacity of the relevant functional block increases. In addition, if a functional block is used that has a circuit configured to increase drive capability and reduce delay time from the beginning, power consumption will increase. However, there was a drawback that the degree of freedom in circuit configuration was reduced.

[Means to solve the problem]

The present invention provides an input/output circuit area having an output section in which a plurality of bipolar transistors are arranged and forming an output stage of a gate array, and a P- and N-channel MOS for driving the bipolar transistors in the output section and providing logic. - In a master slice type large-scale integrated circuit having an internal cell area in which transistors are arranged and internal cells constituting a functional block are provided, the MO for driving the bipolar transistor is
A feature is that a plurality of S transistors are arranged in parallel so that an arbitrary number of S transistors can be connected in parallel.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of one embodiment of the present invention.

This embodiment is a Bi-CMOS type, and includes an internal cell 1 and its internal cells that can configure a circuit in which MOS transistors for driving bipolar transistors in the output stage are arbitrarily connected in parallel according to differences in load capacitance. It has an internal cell area 2, an input/output circuit area 3, and a bonding pad 4 that are arranged in a plurality of repetitions.

FIG. 2 is a circuit diagram of an example of an inverter.

This circuit is intended to be incorporated into the embodiment shown in FIG. 1 as a functional block. In Figure 2, 5 and 6 are NPN transistors, 7 and 8 are P-channel MOS transistors, 9, 10 and 11 are N-channel MOS transistors, 12 is a resistance element, 13 is a power supply terminal, 14 is an input terminal, and 15 is an output Indicates terminal.

After determining the layout of the functional blocks on the chip and the wiring pattern, if the load capacitance of the relevant functional block is small, connect the P-channel MOS transistor 7 between the base of the NPN transistor 5 and the power supply terminal 13, and connect the NPN transistor 6. For driving, the N-channel MOS transistor 10 connected between the base of the NPN transistor 6 and the output terminal 15 is simply connected, but if the load capacitance of the corresponding functional block is large, the delay time will also increase. Therefore, when high-speed operation is required, P channel M
A P-channel MOS transistor 8 is connected in parallel with the OS transistor 7, an N-channel MOS transistor 11 is connected in parallel with the N-channel MOS transistor 10, and the P-channel MOS transistor and NPN are connected between the base of the NPN transistor 5 and the power supply terminal. transistor 6
By connecting the MOS transistors in parallel, the on-resistance when the N-channel MOS} radiator is turned on between the base and the output terminal of the NPN transistors is reduced, and faster operation is possible by turning on the NPN transistors 5 and 6 earlier.

FIG. 3 is a plan view of the circuit shown in FIG. 2 formed on a semiconductor chip.

The circuit shown in FIG. 2 is formed on a semiconductor chip using the master slice shown in FIG. A resistance element 12 and NPN transistors 5 and 6 are configured in one basic unit of the internal cell 1, ]6 and 17 are collectors, ]8 and 19
indicates the emitter, 2o and 21 indicate the base and the contacts with the aluminum wiring, respectively, and regions 22 and 2
4 constitutes an N-channel MOS transistor, and the region 22
constitutes a P-channel MOS transistor.

25 and 26 are gate electrodes shared by P and N channel Mos transistors, 27 and 28 are N channel MO transistors.
This is the gate electrode of the S transistor. The seal is MOS
Indicates the source, drain, and gate of a transistor, or the contact between a resistive element and aluminum wiring,
29 and 3o are GND potential wirings, and 1 is a power supply potential wiring.

Most to drive the bipolar transistor in the output stage
Depending on the difference in load capacity, two circuit configurations are possible, one in which two transistors are connected in parallel and one in which they are not connected in parallel. In this case, layout patterns corresponding to these two circuits must be prepared, but the common part of these two layout patterns is used as the basic form of the functional block,
After determining the layout of the functional blocks on the chip and determining the wiring pattern, the circuit intended by the present invention can be easily configured on the chip by overlapping contacts and aluminum wiring according to the difference in the load capacity of the corresponding blocks. becomes.

FIG. 4 is a plan view showing a basic layout in which the layout of circuit elements and wiring shown in FIG. 3 is constructed by functional blocks.

Contacts 32, 33, 34 and aluminum wiring 35.
36 patterns, a circuit in which the P channel MOS transistor 8 and the N channel MOS transistor 11 in the circuit diagram of FIG. 2 are not connected is constructed on the chip. At this time, the gate electrode 27 is connected to the ground potential by the contact 34 and the aluminum wiring 35 to prevent accumulation of charge, and the same applies when the circuit is constructed on the circuit chip shown in FIG. 2.

From the above, in the internal cell of Bi-CMOS type, MOS for driving the bipolar transistor}
After determining the layout of the functional blocks on the chip and determining the wiring pattern, it is possible to configure a circuit in which radiators are arbitrarily connected in parallel according to the difference in load capacitance.

Although this embodiment concerns the circuit shown in FIG. 2, the present invention can also be applied to the MOS transistor that drives the bipolar transistor in the output stage in other Bi-CMOS circuits. . Further, in this embodiment, an example of an inverter circuit is shown, but other logic circuits are also applicable. Furthermore, in this embodiment, the MOS}radiator that drives the bipolar transistor in the output stage is
Although these are connected in parallel, it is clear that any number of them may be connected in parallel. Further, in this embodiment, the present invention is applied to increase the speed when the load capacity increases in a functional block, but the present invention is not limited to this, and the present invention is also applied to a desired functional block to increase the speed. It is possible to shorten the time.

〔Effect of the invention〕

As described above, the present invention provides a mask slicing type gate array LSI in which when BiCMOS type internal cells are configured, MOS transistors for driving the piezoelectric transistors in the output stage of the functional blocks can be arbitrarily selected. By configuring a circuit in which the number of transistors is connected in parallel, it is possible to reduce the delay time when the load capacity is large or when high-speed operation is required.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of an inverter, FIG. 3 is a plan view of the circuit shown in FIG. 2 formed on a semiconductor chip, and FIG. Figure 3 is a plan view showing a basic layout when configuring the layout of circuit elements and wiring shown in functional blocks, and Figure 5 is a plan view showing a basic layout in which functional blocks are constructed based on the basic layout shown in Figure 4. A plan view of the layout. FIG. 6 is a plan view showing an example of a conventional gate array LSI. 1... Internal cell, 2... Internal cell area, 3... Input/output circuit area, 4... Bonding pad, 5, 6...
・NPN transistor, 7.8...P channel MOS
Transistor, 9, 10, 11...N channel MOS
Transistor, 12... Resistance element, 13... Power supply terminal, 14... Input terminal, 15... Output terminal, 16, Co, 7... Contact between collector and aluminum wiring, 18.19...・Contact between emitter and aluminum wiring, 20.21... Contact between base and aluminum wiring, 22... Areas forming P channel MOS transistor, 23.24... N channel M
Region configuring the OS transistor, 25, 26...P
and N-channel MOS transistor shared gate electrode, 27.28... Gate 1 electrode of N-channel MOS transistor, 29.30... GND potential wiring, 31.
・Power potential wiring, 32, 33. 34... Contact, 3
5.36...Aluminum wiring, 37...LSI chip.

Claims (1)

[Claims] an input/output circuit area having an output section in which a plurality of bipolar transistors are arranged and forming an output stage of a gate array;
A master slice type large-scale integrated circuit having an internal cell region in which P and N channel MOS transistors for driving the bipolar transistor of the output section and providing logic are arranged and internal cells constituting a functional block are provided. A large-scale integrated circuit, characterized in that a plurality of the bipolar transistor driving MOS transistors are arranged in parallel so that an arbitrary number of the bipolar transistor driving MOS transistors can be connected in parallel according to the load capacitance of the functional block.