JPH02288721A - Phase adjustment circuit - Google Patents

Abstract

PURPOSE:To adjust the timing so as to surely receiver a serial data by comparing a latched data with an internally stored data equal to a serial data prepared in advance and controlling the delay time based on the result of comparison. CONSTITUTION:A host circuit sends the same data pattern as an 8-bit data stored in the internal register of a microcomputer 5 in advance as a serial data (a). The microcomputer 5 sets the delay time of the serial data by using a delay selection signal (d) to release a reset signal (f), a parallel data (k) is read by awaiting the time when a parallel data (j) is latched and the data is compared with an internal data pattern. The operation above is repeated for several number of times, and the delay time of a delay selection circuit 1 is fixed by using a delay selection signal (d) to the delay time in which the internal data pattern and the fetched parallel data pattern are completely coincident with each other. After the selection signal is fixed, a phase adjustment end signal (i) is sent to the host circuit to complete the phase adjustment of the serial data (a).

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase adjustment circuit, and more particularly to a phase adjustment circuit that adjusts the phase between an acquisition clock and serial data when handling serial data.

(Conventional technology) Conventionally, when importing serial data using tarokku,
The side sending serial data simply maintains a fixed phase relationship between the serial data and the clock, and the receiving side does not adjust the timing.

(Problem to be Solved by the Invention) The conventional serial data convergence method described above has the disadvantage that if nothing is done on the receiving side, the data acquisition will fail when the phase relationship changes due to wiring delays, etc. be. Another drawback is that the serial data cannot be received unless the serial data transmitter and receiver have the same clock.

(Means for Solving the Problems) A phase adjustment circuit according to the present invention includes a delay selection circuit that delays the phase of predetermined serial data by an arbitrary time, and a shifter that receives the serial data delayed by the delay circuit at clock timing. a register, a latch circuit that latches the output of this shift register, a flip-flop that generates a latch signal for this latch circuit, and internal storage that is equal to the data latched by the latch circuit and the predetermined serial data prepared in advance. and a control circuit that compares the data and controls the delay time of the delay selection circuit based on the comparison result.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block circuit diagram showing one embodiment of the phase adjustment circuit of the present invention.

Serial data a is input to delay selection circuit 1 from an external circuit (not shown). On the other hand, the clock b is input to the shift register 2 from an external circuit (not shown) and is also sent to an external circuit (data receiving circuit) not shown. The serial data a is delayed in the delay selection circuit 1 by a delay selection signal d sent from the microcomputer (control circuit) 5, and is sent as serial data C to the shift register 2 and the above external circuit (data receiving circuit).
sent to. Serial data C in shift register 2
is fetched at clock b and sent to latch circuit 4 as parallel data j. Shift register most significant bit signal e
is input to the flip-flop 3 in order to send a latch signal g to the latch circuit 4. The output of the latch circuit 4 is input to the microcomputer 5. The reset signal f output from the microcomputer 5 resets the shift register 2 and the flip-flop 3, and the phase adjustment completion signal i is connected to an external circuit (not shown).

The phase adjustment start signal is a signal from an external circuit and is input to the microcomputer 5.

First, a higher-level circuit (not shown) notifies the microcomputer 5 of the start of phase adjustment using a phase adjustment start signal, and at the same time, stores the phase adjustment start signal in advance in the internal register of the microcomputer 5.
The same data pattern as the toot data, for example “too
Serial data a repeating pattern such as "otooo"
Send as. When the microcomputer 5 receives the phase adjustment start signal, it sets the delay time of the serial data using the delay selection signal d and releases the reset signal f.

The delayed serial data C is a signal obtained by delaying the serial data A by the time set by the microcomputer 5.
The signal is sent from the delay selection circuit 1 to the shift register 2. Shift register 2 receives serial data C at clock b. When "1" of the serial data C reaches the most significant bit, the shift register's most significant bit signal e causes the flip-flop 3 to become "1", and the latch signal g causes the latch 4 to latch the parallel data j. After releasing the reset signal f, the microcomputer 5 waits for a time for the parallel data j to be latched, reads the parallel data k, and compares it with the internal data pattern. At the same time as the comparison, a reset signal is sent to the flip-flop 3 and shift register 2 through the reset signal f, and the flip-flop 3 and shift register 2 are reset.

After repeating the above operation several times and fixing the 0 selection signal that fixes the delay time of the delay selection circuit 1 with the delay selection signal d at a delay time where the internal data pattern and the imported parallel data pattern completely match, the upper circuit Then, a phase adjustment end signal l is sent to end the phase adjustment of the serial data a.

(Effects of the Invention) As explained above, the present invention automatically adjusts the phase of serial data without considering the phase relationship between the serial data and the clock for importing serial data from the outside, and provides a reliable system. Data can be imported. Furthermore, even if the clock is not the one on the serial data sending side, if the clock cycle is the same, phase adjustment can be performed to adjust the timing to ensure that the serial data can be received.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram showing an embodiment of a phase adjustment circuit according to the present invention. DESCRIPTION OF SYMBOLS 1...Delay selection circuit, 2...Shift register, 3...Flip-flop, 4...Latch circuit, 5...Microcomputer.

Claims (1)

[Claims] A delay selection circuit that delays the phase of predetermined serial data for an arbitrary period of time, a shift register that receives the serial data delayed by this delay circuit at clock timing, a latch circuit that latches the output of this shift register, and this latch. A flip-flop that generates a latch signal of the circuit compares the data latched by the latch circuit with internally held data prepared in advance that is equal to the predetermined serial data, and based on the comparison result, the delay selection circuit and a control circuit for controlling the delay time of the phase adjustment circuit.