JPH02288237A - Manufacture of thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In order to prevent the generation of gaps between a channel protective film and source and drain electrodes with respect to thin film transistors with few short-circuit defects, After forming a gate electrode with a pattern of , a gate insulating film covering the gate electrode, an active semiconductor film (3), and a channel protective film are laminated in this order, and then aligned with the gate electrode on the channel protective film. a step of forming an overhang-shaped resist film with a top extending like an eave; a step of performing anisotropic etching on the channel protection film using the resist film as a mask; and removing the eaves portion of the resist film. After performing the process and the process of forming a source/drain electrode film, the resist film is removed and an unnecessary film attached on the resist film is lifted off.

[Industrial Application Field] The present invention relates to a thin film transistor with few short circuit defects.

In recent years, thin film transistor matrices using thin film transistors as switching elements for driving pixels have been commercialized as liquid crystal display panels, pocket TVs, and display devices for information terminal devices.

In order to commercialize this thin film transistor matrix, it is necessary to manufacture it at low cost and with high yield, and when used for information terminals, there is a risk that even if there are - number of point defects, it will be interpreted as incorrect information. Therefore, it is necessary to manufacture a large number of devices without defects.

In order to manufacture a thin film transistor matrix in which a large number of elements are arranged in a matrix without causing defects, it is necessary to be able to manufacture it through a simple process.

[Conventional technology]

The conventional method for manufacturing thin film transistors is shown in Figures 3(a) to (3).
f).

First, a gate electrode G is formed on a glass substrate L [same figure (
See a)].

Next, a gate insulating film 2. is formed by plasma chemical vapor deposition (P-CVD). Operating semiconductor film 3. Channel protective film 4
[See figure (b)] Next, a resist film 5 is formed which serves both as a channel protective film etching and a source/drain electrode lift-off [
See figure (C)].

Using this resist film 5 as a mask, the channel protective film 4 other than the channel portion is removed [see FIG. 4(d)].

Next, contact layer 6. After forming the source/drain electrode film 7, the resist film 5 is removed, and the contact layer and the source/drain electrode film deposited thereon are lifted off [see FIG. 4(e)].

The conventional thin film transistor created as described above is
As shown in FIG. 4(f), a channel protective film 4 and a source electrode S. A gap is created between the drain electrode and the drain electrode. This occurs because the resist film used for etching the channel protection film 4 and the resist film used during lift-off are the same.

[Problem to be solved by the invention]

In this way, the channel protective film 4 and the source electrode S.

If a gap is created between the drain electrode and the drain electrode, cracks will occur in the gate insulating film due to mechanical and physical stress in the gap, resulting in a short circuit between the gate electrode G, source electrode S, and drain electrode. occurs.

An object of the present invention is to prevent the generation of gaps between a channel protective film, a source electrode, and a drain electrode.

[Means to solve the problem]

The present invention involves stacking a gate insulating film, an active semiconductor layer, and a channel protective film on a gate electrode formed on an insulating substrate, and then depositing a resist layer on top of the gate insulating film, which is aligned with the gate electrode and has an overhang-shaped cross section. Forms a film.

Using this resist film as a mask, anisotropic dry etching is applied perpendicularly to the surface of the channel protective film.Then, the eaves of the resist film is removed, and a film formation process for forming source and drain electrodes is performed. , removing the resist film.

[For production]

In the present invention, the resist film is formed in an overhang shape. In other words, the top of the resist film has a cane shape with an eave extending beyond the portion in contact with the channel protection film.

Since the channel protective film is etched by an anisotropic etching method using this resist film as a mask, not only the portion of the channel protective film in contact with the resist film but also the area directly under the eaves of the resist film is masked. Therefore, the channel protective film remains with its peripheral portion exposed.

After this etching, with the resist film from which the eaves portion has been removed remaining on the channel protective film, a film formation process for forming the source/drain electrodes is performed, thereby removing the exposed periphery of the channel protective film. A source/drain electrode film is also deposited thereon. Therefore, the peripheral edge of the channel protection film and the ends of the source/drain electrodes overlap.

As a result, in the thin film transistor manufactured using the present invention, there is no gap between the edges of the source/drain electrode and the edge of the channel protective film, so even if subjected to mechanical stress or physical stress, the gate Cracks are less likely to occur in the insulating film, and short circuit defects are reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1(a) to 1(g).

The steps shown in Figures (a) and (b) are the same as before.

That is, on an insulating substrate such as the glass substrate 1, a thickness of approximately 8.
A gate electrode made of a 0 nm Ti film is formed, and then
On top of that, there is a gate insulating film such as a SiN film 2 with a thickness of about 300 nm, an operating semiconductor film such as an a-Si film 3 with a thickness of about 1100 nm, and an S film with a thickness of about 1100 nm as a channel protection film.
The iO□ film 4 is continuously formed by plasma chemical vapor deposition (P-CVD).

Next, as shown in FIG. 4C, an overhang-shaped resist film 5 is formed on the Sing film 4 in alignment with the gate electrode G.

The resist film 5, which is aligned with the gate electrode G and has an overhang shape, is obtained by subjecting a positive resist coated on the channel protective film 4 to back exposure using the gate electrode G as a mask, and then exposing the positive resist film 5 to a compound such as chlorobenzene or toluene. a
It can be formed by immersing in a solvent for a predetermined time and then developing.

When the resist film is immersed in the organic solvent as described above, the organic solvent permeates into the resist film from the surface, and the permeated portion becomes difficult to be attacked by the developer. Therefore, even in non-exposed areas that do not dissolve in the developer, there is a difference in solubility in the developer, and during the development process, there are more areas below where the organic solvent has not penetrated than the surface area where the organic solvent has penetrated. As a result, an overhang-shaped resist film with the top protruding like an eave is obtained.

Note that the step of immersing in an organic solvent may be performed before or after exposure.

Using the overhang-shaped resist film 5 thus formed as a mask, a reactive ion etching method using CF, /H, and plasma, which is an anisotropic dry etching method with linearity, is applied to SiO□ Etch the film 4.

During this etching process, not only the portion of the 5ift film 4 hidden by the resist film 5 but also the portion shaded by the eaves around it are masked. Therefore, the Si, O, film 4 is formed in a shape with the peripheral edge exposed, as shown in FIG. 4(d).

Next, the resist film 5 is subjected to reactive ion etching using oxygen plasma, as shown in FIG.
As shown in FIG. 3, a predetermined thickness of the top of the resist film 5 is removed to remove the eaves.

Next, as shown in FIG. 2F, an n''a-3i film 6 is formed to a thickness of about 30 nm as a contact layer, and a Ti film 7 is formed to a thickness of about 1100 nm as a source/drain electrode film.

The nr”as+ film and Ti film formed here are S
In, it is also deposited on the exposed periphery of the membrane 4. Therefore,
The ends of the source electrode S and drain electrode are made of SiO□
It overlaps the peripheral edge of the membrane 4, and no gap is created between the two.

After that, the resist film 5 is removed, and the n''
Unnecessary portions of the a-3i film 6 and the Ti film 7 are lifted off, and the TPT according to this embodiment is completed as shown in FIG. 4(g).

According to this embodiment, since no gap is formed between the source electrode S and drain electrode S and the channel protective film 4, cracks in the gate insulating film due to mechanical and physical stress are prevented. The occurrence of defects is reduced and reliability is improved.

Next, FIG. 2 shows another embodiment of the present invention.

In this embodiment, as seen in the figure, the channel protective film 4 has a two-layer structure in which the SiO□ film 41 is the lower layer 1 and the SiN film 42 is the upper layer.

That is, about 20 nm of SiOz film 41 is placed on the a-3i film 3.
SiN with a thickness of about 1100 nm is formed on top of the SiN film with a thickness of about 1100 nm.
The films 42 are stacked, and the upper SiN film 42 is first etched using a reactive ion etching method using the overhanging resist film 5 as a mask. After removing the overhang of the resist film 5, it is etched with a buffered hydrofluoric acid solution. The underlying Sing film 41 is etched.

The subsequent steps may proceed in the same manner as in the embodiment described above.

In this example, the surface of the a-3i film 3 is not directly exposed to plasma, and the etching for exposing the a-3i film 3 is a wet etching method.
This has the effect that the interface between the 3i film 3 and the n''a-3i film 6 can be maintained in good condition.

In this embodiment as well, the peripheral edge of the channel protection film and the ends of the source electrode S and drain electrode overlap, and no gap is created between them, as in the above embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, the gap between the channel protective film and the source electrode and drain electrode can be eliminated.
Since cracks are less likely to occur in the gate insulating film even when subjected to mechanical or physical stress, short circuit defects can be prevented from occurring.

[Brief explanation of drawings]

Figures 1(a) to ((to) are explanatory diagrams of one embodiment of the present invention, Figure 2 is an explanatory diagram of another embodiment of the present invention, and Figures 3(a) to (f) are diagrams of conventional TPT. This is a diagram explaining problems in the manufacturing method. In the figure, 1 is an insulating substrate (glass substrate), 2 is a gate insulating film (SiN film), 3 is an active semiconductor film (a-3i film), and 4 is a channel protective film. (Sin film), 5 is a resist film, 6 is a contact layer (n+a-
3T film), 7 is a source/drain electrode film (Ti film), G
is the gate electrode, S is the source electrode, D is Fig. 1 (my 2) Fig. 1 (η's 1) Problem light, the first Pth figure 3rd
Diagram (child 2)

Claims (1)

[Claims] A predetermined pattern of gate electrodes (
G) and a gate insulating film (
2) After laminating the operating semiconductor film (3) and the channel protective film (4) in this order, an overhang-shaped resist film is formed on the channel protective film, the top of which is aligned with the gate electrode and whose top part protrudes like an eave. (5), a step of performing anisotropic etching on the channel protection film using the resist film as a mask, a step of removing the eaves portion of the resist film, and a source/drain electrode film (7). A method for manufacturing a thin film transistor, comprising: removing the resist film and lifting off an unnecessary film attached on the resist film.