JPH02287828A - Prefetch control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 3) Means for solving the problem to be solved by the invention (Figure 1) Working example fa) One implementation Explanation of an example (Fig. 2) (b) Explanation of another embodiment Effect of the invention [Summary] Achieving a system throughput regarding a prefetch control method in which instructions, etc. are fetched in advance from memory in response to a prefetch request from a processor. 1", and in advance the instructions and data from the bank-divided memory are prefetched into the buffer memory in response to a prefetch request from the processor. Detection for detecting a bank busy failure in the memory in the 7-chi uncontrollable method. and a comparison means for comparing the detected bank busy number with a predetermined value. Prefetch requests are now suppressed or canceled.

[Industrial application field]

The present invention relates to a prefetch control method in which instructions, etc. are prefetched from memory in response to a prefetch request from a processor.

Prefetch (first 11 fetch) control is known as one of advance control techniques for operating a processor at high speed.

Pre-fetching is the process of reading out instructions and data that are likely to be needed in the future from main memory to a high-speed buffer in advance, thereby performing the reading and current processing in parallel, and is also called pre-fetch control. ing.

Such prefetch control preempts instructions that are likely to be needed in the future, so if it is performed in large quantities, it will increase the busy state of the memory, so countermeasures are required.

[Conventional technology] FIG. 3 is an explanatory diagram of the prior art.

In FIG. 3(A), ■ is a processor, 2 is a memory control unit, 3 is a main memory divided into banks, and 10 is a prefetch buffer.

In the prefetch operation, the memory control unit 2 accesses the main memory 3 in response to a prefetch request from the prosensor 1, and stores commands and data in the preemptive rehabilitation sofa 10 in advance.

Since this access by the processor 1 has locality, the data around the accessed address is automatically read out from the memory 3 by hardware to improve the immediacy of reading of subsequent instructions and the history of the prefetch buffer 10.
− We are trying to improve the ratio.

Bluff like this 1. The memory controllers I-roll unit ν1 and ν2 that perform the i wholesale receive the prefetch request from the processor 1, as shown in FIG. 3 (13).
J Robo 1-20-0 ~ 20-n and Bau +-2 (]
- (A priority circuit 21 that determines the priority of prefetch requests accepted in 1 to 20-n, a register 22 that stores requests that have acquired priority, and access to the memory 3 in response to requests from the register 22. A bank busy control circuit 23 identifies the bank that has been accessed and issues a busy signal for that bank.
It has

Then, in response to a request from the register 22, a bank access to the main memory 3 is made, and the bank busy signal of the bank busy control circuit 23 causes the IΩ priority circuit 21 to access the main memory 3.
Requests to the bank are suppressed and conflicts are prevented.

[Problem to be solved by the invention]

However, since prefetch operations are not performed based on actual processing operations, if a large number of prefetch operations are performed, the busy state of the main memory 3 will increase.

This obstructs the access that is originally required for processing.
It delays the original processing and causes system problems.
There was a problem that - worsened.

Therefore, the present invention improves system throughput I-1.
The purpose of LI is to provide a first method of prefetch piracy that can perform prefetching based on the following conditions.

[Means to solve the problem] FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, the present invention uses a prefetch control method in which instructions and data are prefetched from a memory 3 divided into banks into a buffer memory 10 in response to a prefetch request from a processor 1. Detection means 24 for detecting a busy fault, and comparison means 25 for comparing the detected bank busy number with a predetermined darkness value.
and when the comparison means 25 determines that the bank busy number is equal to or higher than the dark value, the received prefetch request is suppressed or canceled.

[Effect]

In the present invention, when the usage rate of memory 3 becomes high due to a request, the prefetch request is suppressed and the prefetch requirement is made to wait for a certain period of time until the usage rate decreases, or the prefetch request is suppressed. The usage rate of the memory 3 due to prefetching is suppressed by canceling the prefetch request itself.

In order to detect the usage rate of the memory 3, it is sufficient to detect the bank busy condition of the memory 3, and by adding a small amount of hardware, prefetching that does not reduce the system throughput becomes possible.

(Example] (a) Description of one embodiment FIG. 2 is a detailed explanatory diagram of the present invention.

In the figure, the same parts as those explained in FIG. 1 and FIG. 53 are indicated by the same symbols.

The bank busy control 11 circuit 23 includes a decoder 23a that decodes the prefetch request of the register 22 and outputs which bank of the memory 3 is to be accessed;
is set when the corresponding bank is accessed by the output of
Flip-flops FFI to FFI for the number of banks E that output the bank busy signal to the priority circuit 21! , and shifts the request of the register 22, and generates a bank busy reset signal at the end of one cycle of the memory 3, m for one cycle.
control pipeline 23b, and control pipeline 23b.
It has an OR circuit OR which takes the OR of the two bank busy/reset 1 signals.

The detection circuit 24 is constituted by a counter, counts up by the activation signal of the register 22 to the memory 3, counts down by the OR signal of the bank busy/reset signal of the control pipeline 23b, and counts the current bank busy fault.

The comparison circuit 25 has a dark value (MBMAX
) is set, and a comparator 25b which compares the bank busy number of the counter 24 and the threshold value MBMAχ of the register 25a and outputs an output if the bank busy number exceeds the threshold value. Depending on the comparison output, the selection of the prefetch request in the priority circuit 21 is suppressed as shown by the solid line, or the selection of the prefetch request is suppressed as shown in the dotted line.
Resetting the prefetch requests from 0-0 to 20-n,
Cancel.

To explain the operation of this configuration, a prefetch request from a certain processor 0 to n is sent to the corresponding processor 20-0 to 20-20.
-n, is selected according to the priority by the priority winding B21, and is set in the register 22.

The request from the register 22 activates and accesses the main memory 3, and at the same time, the decoder 23a decodes which bank is to be accessed, and one of the hang-compatible flip-flops FFI to FFf is set.

By setting the flip-flops FF I to FF ffi, a bank busy signal for the bank is output, and the priority circuit 21 suppresses a prefetch request to the bank.

At the same time, the prefetch request just accessed is input to the control pipeline 23b.

The control pipeline 231] is for -machine cycles, so when the prefetch request passes through the control pipeline 23b due to the shift, it means that the access to the bank has ended, and a bank busy reset signal is issued.

This bank busy reset 1- signal causes the flip-flops FF 1 to FF of the corresponding bank! is reset, the hank busy word is turned off, and the inhibition of selection of the bank by the priority circuit 21 is released.

On the other hand, the counter 24 performs count amplification based on the start signal from the register 22 to the memory 3, and the control pipeline 23
OR circuit of two bank busy/reset signals of b
The countdown is based on the OR signal.

Therefore, the counter 24 counts (number of activated banks - number of completed accesses), that is, the number of currently used banks (number of banks busy) every moment.

The comparison circuit 25 compares the number of hunk elbows in the counter 24 with the threshold (i1'l: M 13 MΔX) in the register 25a, and when the bank busy number exceeds the dark value MBMAX, the prefetch is sent to the priority circuit 2I as shown by the solid line. A request suppression output is added, and the selection of a prefetch request is made to wait until the number of bank busy decreases.

Also, as another method, the comparison output of the comparison circuit 25 is sent to the boats 20-0 to 20-n as shown by the dotted line.
The prefetch request itself may be reset and canceled.

Since the number of banks in the main memory 3 is generally 2" and 47.y, the counter 24 and the register 25a have at most P bits, and even if the comparator 25b is added, the system throughput can be reduced by adding a small amount of hardware. Brif y-7 that does not reduce the OJ ability.

(b) Description of other embodiments - 1 - In the embodiment described above, an example of a system in which a plurality of processors share one main memory was explained, but a single processor may also be used. , also prefetch system @′
Although the example in which the I1 mechanism is provided in the memory controller 2 has been described, it may also be provided in the processor 1.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained below-1-, according to the present invention, the following effects are achieved.

■ When the bank busy number is above the threshold, the memory usage rate is considered high and prefetching is suppressed or canceled, so the memory usage rate does not reach the dark value level and the system does not interfere with the original access. This has the effect of enabling prefetch control with excellent throughput.

(2) Furthermore, since the memory usage rate is detected by detecting the bank busy number, the function can be realized by adding a small amount of hardware, and the function can be added easily and at a low cost.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention. FIG. 2 is a detailed explanatory diagram of the present invention, FIG. 3 is an explanatory diagram of the prior art. In the figure, 1-processor; 2-Memory control 3- Main memory, IO-buffer memory, 24-detection circuit; 25-Comparator, ￥3゜ Ruunint,

Claims (1)

[Claims] In a prefetch control method in which instructions and data are prefetched from a bank-divided memory (3) into a buffer memory (10) in response to a prefetch request from a processor (1), the memory (3) Detection means for detecting bank busy failure (
24), and comparison means (25) for comparing the detected bank busy number with a predetermined dark value, and when the comparison means (25) determines that the bank busy number is equal to or higher than the dark value, . A prefetch control method characterized by suppressing or canceling an accepted prefetch request.