JPH02285597A - Non-volatile semiconductor storage - Google Patents

Abstract

PURPOSE:To read data at high speed by controlling the operation of a '1' read side output transistor in a data output buffer so as to be delayed to a '1' read time at maximum when the data are accessed according to the change of a row address input in the case that the data are accessed according to the change of a column address input CONSTITUTION:When the data are accessed according to the change of the column address input, a column address transition detecting circuit CATD generates a column address transition detection output and pulse width modulat ing circuit PWM generates the pulse output signal of prescribed pulse width. Then, a control circuit CONT executes control so as to delay the '1' read operation of a data output buffer OB. Accordingly, when a selected column line is initially set to a ground potential and a selected memory cell is set in a turning OFF state, the '1' reading of the data output buffer OB is delayed even in the case that the glitch of '0' '1' '0' is generated in the output of a sense amplifier. Thus, the delay of an internal circuit can be suppressed as much as possible and the delay of '0' reading for the output of read data can be suppressed as much as possible. Then, the data can be read at high speed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor non-volatile memory device, and particularly relates to a method for outputting read data at the time of access when the column address power of the memory device changes. This invention relates to a technique for preventing glitches at the "o" → "1# → "0" level from occurring.

(Prior art) Conventional semiconductor read-only memory device (hereinafter referred to as ROM)
, for example, CMO8 type (complementary insulated gate type) mask R
A portion of the OM is shown in FIG. That is, 1-11 to l
-m n is a ROM cell arranged in a matrix of m rows and n columns, each consisting of an N-channel MO3) transistor whose source is connected to the ground potential VSS, and whose gate threshold is "O" of the stored data. 1".

In the memory cell array MA in which ROM cells 1-11-1-mn are arranged in rows and columns, WL1 to WL
m is a driving line commonly connected to the gates of ROM cells in the same row, and BLI to BLn are column lines commonly connected to the drains of ROM cells in the same column. RD is a row decoder that selects the above batting line according to the row address input; C8
Column selection transistors 1 to C3n are connected in series to the column lines BLI to BLn and have their other ends connected in common, and are each made of, for example, an N-channel MO3+- transistor. CD is a column decoder that selects column selection transistors C8I to C8n in accordance with a column address input.

Between the Vcc'rlf source (for example, 5V) and the common connection point (common column line) of column selection transistors CS'1 to C3n, there is an N-channel MOS transistor QL for load whose drain and gate are connected to each other. It is connected. Also,
10. The common column line is connected to the input end of a sense amplifier SA that detects and amplifies the read signal. OB is a data output buffer that amplifies the output of the sense amplifier SA.

Next, the normal read operation of the ROM will be explained with reference to FIG. Here, it is assumed that the design is such that the high level/low level of the potential of the selected column line corresponds to the "0" level (low level)/"1" level (high level) of the read data output. .

At the time of access when the row address input changes without changing the column address manually, the potential of each column line connected to each memory cell selected by the row selection is changed to whether the selected cell is in the off state (memory data "0"). For example, in the case of 3
．． High level of 5V (higher level than sense amplifier judgment base), selected cell is on state (memory data "1" state)
In this case, the voltage is at a low level of, for example, 2.5V (a level lower than the sense amplifier judgment standard). That is, the potential of the column line connected to the selected memory cell is 1] 2.2.5
and 3.5V, the read data output changes between “1” and “O”, and “1” → “0” or “1” → “1” or “0” → “0” or “O”
→ Changes like “1″’.

On the other hand, during access when the column address input changes while the row address input remains the same, the read data output corresponding to the level of the column line connected to the selected memory cell appears, and the read data output is “1” → “0”
"or changes like "1"-"1" or "0"→"0" or "0"-"1".

However, when accessing - due to a change in the array address input, the column line may be initially set to the ground potential (for example, the potential of the column line may drop to the ground potential due to junction leakage current of each cell). , and when the selected memory cell is in the off state, the read potential from the selected column line once drops to a low level and then returns to its original high level. Therefore, the read data output in this case is
It does not change from "0" to "0" like the access when the row address input changes as described above, but "
1", and a change (glitch) from "0" to "1" to "02" occurs.

In this way, when "1" is transiently generated in the read data output, the potential level of the read data output is temporarily lowered due to the parasitic inductance and parasitic resistance existing in the power supply wiring of the chip. Moreover, since the capacitance connected to the data output terminal is large, two successive power supply potentials seen from the ground potential of the chip are bundled together. In this case, the first fluctuation occurs just when the sense amplifier is about to read the potential of the selected column line, so the delay in the internal circuit increases, causing a significant delay in reading "0" from the read data output. , access time will be slower. Ideally, the sense amplifier output should be “0”.
It would be nice if it could be possible to prevent the glitch of →“]”→“0” from occurring, but that is difficult.

The same thing can be said about other ROMs.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor nonvolatile memory device, a glitch at the "O"-"1"-"0" level occurs in the read data output when accessing due to a change in the column address input. Therefore, there is a problem that the internal circuit delay increases, the reading of "0" of the read data output is significantly delayed, and the access time becomes slow.

The present invention has been made to solve the above-mentioned problems, and its purpose is to prevent glitches from occurring in the sense amplifier output from 40'' to 1 to 0 when the column address input changes. Another object of the present invention is to provide a semiconductor non-volatile memory device that can suppress delays in internal circuitry as much as possible, can suppress delays in reading "0" of read data output as much as possible, and can realize high-speed reading.

[Structure of the Invention (Means for Solving the Problems) The present invention provides a memory cell array in which nonvolatile memory cells are arranged in m rows and n columns, and selects m dot lines of this memory cell array. a row decoder, a column selection transistor for selecting 0 column lines of the memory cell array, and a column decoder for controlling the column selection transistor;
In a semiconductor non-volatile memory device that includes a sense amplifier that detects and amplifies a read signal from a selected column line that has passed through a column selection transistor, and a data output buffer that buffers and amplifies the output of this sense amplifier, it is possible to A column address transition detection circuit for detecting, a pulse width modulation circuit for generating an output signal of a predetermined pulse width by manually inputting the detection output of the column address transition detection circuit, and a pulse width modulation circuit for generating an output signal of a predetermined pulse width, and the output signal of the pulse width modulation circuit for outputting the data. “1” in the buffer
“The device is characterized by comprising a control circuit that controls the read operation to be delayed.

(Function) When accessing due to a change in the column address input, the operation of the “1” read side output transistor of the data output buffer is changed to “1” when accessing due to a change in the row address input.
Even if a glitch from 0 to 1 to 0 occurs in the sense amplifier output, by delaying the reading of 1 from the data output buffer, The influence of fluctuations in the read power supply potential due to changes in the read data output is prevented from being fed back to the sense amplifier system. Therefore, the delay in the internal circuit at this time is suppressed as much as possible, the delay in reading "0" of the read data output is suppressed as much as possible, and the access time is increased.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of a mask ROM, for example.
Compared to the conventional mask ROM described above with reference to FIG. 7, (a) column address transition detection detects a change in the output signal of the column address buffer CAB input to the column decoder CD, that is, a transition of the column address input; The circuit CATD and (b
) A pulse width modulation circuit PWM that receives the detection output of the column address transition detection circuit CATD and generates an output signal with a predetermined pulse width; "The difference is that a control circuit C0NT for controlling the read operation to be delayed is added, and the rest is the same, so the same reference numerals as in FIG. 7 are given.

Next, the operation of the ROM shown in FIG. 1 will be explained. Here, since the normal read operation is basically the same as the operation of R'OM shown in FIG.
The operation of the J addition circuit will be explained with reference to FIG.

During access due to a change in the row address input, the column address transition detection circuit CATD does not generate a column address transition detection output, the pulse width modulation circuit PWM does not generate a pulse output signal, and the control circuit C0NT outputs the data output buffer O.
The "1" read operation of B is not delayed.

On the other hand, when the column address is accessed due to a change in human power, the column address transition detection circuit CATD generates a column address transition detection output, which causes the pulse width modulation circuit PWM to generate a pulse output signal with a predetermined pulse width. , thereby causing the control circuit C0NT to control the "]" read operation of the data output buffer OB to be delayed.

As a result, when accessing due to a change in the column address input, when the selected column line is set to the ground potential and the selected memory cell is in the off state, the sense amplifier output is set to "0" - Even if a glitch from 1" to "0" occurs, the reading of "1" from the data output buffer OB is delayed, so the current that transiently charges the output terminal disappears (or decreases), and the read data output changes. This eliminates (or reduces) the fluctuations in the power supply potential that occur over time.

Even if the read type source potential fluctuates due to changes in the read data output, since at this time it has already been determined that it is the output of the sense amplifier SA, it will not be returned to the sense amplifier system due to the influence of this power supply potential fluctuation. It becomes like this.

Therefore, the delay in the internal circuit at this time is suppressed as much as possible1, 1j, the adverse effects caused by the glitch of "0" → "1" → "O" mentioned above are minimized, and the delay in reading "0" of the read data output is minimized as much as possible. reduced, speeding up access time.

The time it takes to read "1" from the sense amplifier when accessing due to a change in the column address manual power described above is much faster than the time it takes to read "1" when accessing due to a change in the row address manual power, so the data output buffer O
The timing for delaying the "1" read operation of B is access 11.B due to a change in row address input. The delay in reading "1" of "1" may be set to have a linearly proportional relationship with the delay between "1" and "9", and a maximum of "1" readout time during access due to a change in row address input is allowed.

FIG. 3 shows a specific example of the pulse width modulation circuit PWM in FIG. 1, in which the pulse width modulation circuit PWM in FIG. . That is, the input signal (column address transition detection pulse signal inputted from the column address transition detection circuit CATD) a passes through two stages of inverters IVI and IV2, and then passes through the equivalent row decoder ERD and the equally spaced line EWL to the equivalent memory cell ECEL. input into the gate. These equidistant row decoders ERD, equivalent dot lines EWL, and equivalent memory cells ECEL correspond to row decoders RD and dot lines W, respectively.
L1-WLm, memory cells 1-11 to 1-
It has the same configuration as mn. This equivalent memory cell ECE
Column lines BLI to BL are connected between the drain of L and the ground potential.
Equivalent column capacitance ffi E B approximately equal to the parasitic capacitance of n
C is connected.

Also, the drain of the equivalent memory cell ECEL and Vcc? 1
An N-channel MOS transistor TN for load and a P-channel MO transistor TP for activation switch are connected in series between the source and the P-channel MOS transistor TN.
O8) The input signal a is inverted by the inverter IV3 and input to the gate of the transistor TP]3, and the drain potential of the equivalent memory cell ECEL is inverted by the inverter IV4i and input to the gate of the N-channel MOS transistor TN. input.

The input terminal of an equivalent sense amplifier ESA having the same configuration as the sense amplifier SA is connected to the drain of the i1ji memory cell ECEL. -) One input of NRG. Input signal a is input as the other human power of this two-man gate NRG,
The output of this two-person gate NRG is inverter IV6
The signal is then output as a pulse width modulated signal.

Further, between the output side node of the equivalent row decoder ERD and the ground potential, between the output side node of the equidistant stroke line EWL and the ground potential, and between the output side node of the equivalent sense amplifier ESA and the ground potential, respectively. MO for resetting N channel
S transistors TRI, TR2, and TR3 are connected, and MO5I-transistor TRI for resetting them is connected.
An input signal a is input to each gate of ~TR3.

FIG. 4 shows an example of voltage waveforms at various parts during operation of the pulse width modulation circuit PWM. That is, normally, the output side node b of the equivalent row decoder ERD and the output side node C of the equidistant stroke line EWL are at a high level, and the input end node d and output node e of the equivalent sense amplifier ESA are at the ground potential. When the input signal a is input, each of the reset MOS transistors TRI to TR3 is turned on for this input period, and the output side node b of the equivalent row decoder ERD and the output side node C of the equally spaced dot line EWL become ground potential.
The input side node d and output node e of the equivalent sense amplifier ESA become high level.

Thereafter, the output node b of the equivalent row decoder ESA returns to a high level, and after a delay time of the evenly spaced striking line EWL, the output node C of the equally spaced striking line EWL returns to a high level. Furthermore, after a delay time due to the equivalent column line capacitance i1r E B C, the input end node d of the equivalent sense amplifier ESA returns to the ground potential and the output node e returns to the ground potential, so that the output signal with the desired pulse width is This means that you have obtained it.

FIG. 5 shows a specific example of the data output buffer OB and control circuit C0NT in FIG. 1.

That is, the data output buffer OB has one P channel M
O8) A transistor TP and one N-channel MOS transistor TN are connected in series between the vCC power supply and the ground potential, and this series connection point is connected to the data output terminal OUT.

Note that C is a capacitance parasitic to the output wiring. Control circuit C
0NT is a first two-person gate NRG1 to which the output signal of the sense amplifier SA and the output control signal OE are input, and a second two-person gate NRG2 to which the output signal and the output control signal OE of the pulse width modulation circuit PWM are input. ,
It consists of a first two-person NAND game 1-NAG1 into which the output signal of the sense amplifier SA and the output signal of the second two-person gate NRG2 are input.

Then, the output signal of the second two-man NAND gate NRG2 is input to the gate of the N-channel M0S transistor TN of the data output buffer OB, and the first two-man NAND game 1-
The output signal of N A G ] is the data output buffer OB.
is input to the gate of P-channel MO3+- transistor TP.

Therefore, when the output control signal OE is in an inactive state (high level in this example), the first two-person output signal NRG'
1 output signal and a second two-person game-l-N RG
The two output signals each become low level, and the output signal of the first two-man NAND gate NAG1 becomes high level,
Each transistor of the data output buffer OB is turned off, and the output terminal OUT is in a high impedance state. On the other hand, when the output control signal OE is in an active state (low level in this example), the data output buffer OB is driven by the output signal of the sense amplifier SA.

However, in this case, while the output signal of the pulse width modulation circuit PWM is at a high level, the output signal of the first two-way gate NRG1 is at a low level, and the output signal of the first two-way NAND gate NAGI is at a high level. level, the P channel MO3) Langstaff TP is turned off, and the "]" read operation is delayed.

FIG. 6 shows a modification of the data output buffer OB and control circuit C0NT in FIG. 5, and compared with FIG. 5,
The P-channel MO5+- transistor of the data output buffer OB is divided into two (TPI, TP2), and the gate of one P-channel MOS transistor TPI is connected to the output of the first two-way NAND gate NAG1, and the other The gate of the P-channel MO8I-transistor TP2 is connected to the output signal of the sense amplifier SA and the output control signal O.
Second two-man power game 1-N into which the inverted signal of E is input
The difference is that the input is the output of A G 2, and the rest is the same, so the same reference numerals as in FIG. 5 are given.

In the circuit of FIG. 6, when the output control signal OE is inactive (high level in this example), the first two-person gate N
Output signal of RG1 and second two-person gate NRG
The output signals of the first two-person canand gate NAG]81 and the second two-person canand gate NAG2 each become low level.
The outputs R and R become high level, each transistor of the data output buffer OB turns off, and the output terminal OU
T is in a high impedance state. On the other hand, when the output control signal OE is in an active state (low level in this example), the data output buffer OB is driven by the output signal of the sense amplifier SA.

However, in this case, while the output signal of the pulse width modulation circuit PWM is at a high level, the output signal of the first two-man NAND gate NRG1 is at a low level, and the output signal of the first two-man NAND gate NAG1 is at a high level. Therefore, one of the P-channel MO5+- transistor game 1-TP1 is turned off, and the operation of continuously outputting "1" is delayed.

In addition, although the mask ROM was shown in the above embodiment, the present invention is also applicable to ultraviolet erasable and rewritable ROM (EPROM).
or electrically erasable/rewritable RO,M (EEPR
It can also be applied to semiconductor nonvolatile memory devices such as OM).

] 9 [Effects of the Invention] As described above, according to the semiconductor nonvolatile memory device of the present invention, upon access due to a change in column address input,
Even if a glitch of 0" → "12 → "0" occurs in the sense amplifier output, the delay in the internal circuit due to this can be suppressed as much as possible, and the delay in reading "0" of the read data output can be suppressed as much as possible, allowing high-speed reading. It is possible to make it happen.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a part of a ROM according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing an example of a read operation of the ROM in FIG. 1, and FIG. A circuit diagram showing a specific example of a pulse width modulation circuit, FIG. 4 is a diagram showing an example of voltage waveforms at various parts during operation of the pulse width modulation circuit in FIG. 3, and FIG. 5 is a diagram showing the pig output in FIG. 1. FIG. 6 is a circuit diagram showing a specific example of the buffer and control circuit. FIG. 6 is a circuit diagram showing a modification of the data output buffer and control circuit in FIG. 5. FIG. 7 is a configuration explanation showing a part of a conventional ROM. Figure 8 is the RO of Figure 7.
FIG. 6 is a waveform diagram showing an example of a read operation of M. FIG. 1-11~1-mn=-ROM cell, MA-・
Memory cell array, WLI~WLm... batting line, B
L]~BLn...Column line, RD...Row decoder, C8
I~C3n...Column selection transistor, CD...Column decoder, QL...N channel MO5) transistor, S
A...Sense amplifier, OB...Data output buffer, CATD...Column address transition detection circuit, PWM...
・Pulse width modulation circuit, CON 1'...control circuit, E
RD: Equal value stroke decoder, EWL: Equal value stroke line, E
CEL: equivalent memory cell, EBC: equivalent column capacitance ffl, ESA: equivalent sense amplifier. Applicant's agent Patent attorney Suzu/X ni Takeha Tenmi, 0 ■

Claims (2)

[Claims] (1) A memory cell array in which nonvolatile memory cells are arranged in m rows and n columns, and m of this memory cell array.
a row decoder that selects a line to be printed; a column selection transistor that selects n column lines of the memory cell array; a column decoder that controls the column selection transistor; and a readout from the selected column line via the column selection transistor. Detects the signal
A semiconductor non-volatile memory device comprising a sense amplifier for amplification and a data output buffer for buffer-amplifying the output of the sense amplifier, a column address transition detection circuit for detecting a transition of a column address input; a pulse width modulation circuit that receives the detection output of the pulse width modulation circuit and generates an output signal with a predetermined pulse width, and a control circuit that controls the output signal of the pulse width modulation circuit to delay the "1" read operation of the data output buffer. A semiconductor nonvolatile memory device comprising: (2) The pulse width of the output signal output by the pulse width modulation circuit is “1” when accessing due to a change in the column address input.
2. The semiconductor non-volatile memory device according to claim 1, wherein the semiconductor non-volatile memory device has a linearly proportional relationship with a read delay time.