JPH02283016A - Forming method of semiconductor layer containing boron - Google Patents

Abstract

PURPOSE:To form a thin semiconductor layer containing boron by forming an insulating film on a semiconductor layer and ion-implanting boron in the above semiconductor layer via the insulating film. CONSTITUTION:On a semiconductor layer 12, an insulating film 13 is formed, via which boron 15 is ion-implanted in the above semiconductor layer 12. According to this method, while the boron ion 15 passes the insulating film 13, the implantation energy is absorbed by the insulating film 13, and knock-on effect on the insulating film 13 is little because the mass number of boron 15 is small. Further it is possible to form a thin semiconductor layer containing boron.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for forming a boron-containing semiconductor layer, in which the boron-containing semiconductor layer is formed by implanting boron ions into a semiconductor layer.

[Summary of the invention]

In the method for forming a boron-containing semiconductor layer as described above, an insulating film is formed on the semiconductor layer, and boron is ion-implanted into the semiconductor layer through the insulating film. This makes it possible to form a boron-containing semiconductor layer that is thin and whose characteristics are less affected by the insulating film.

The invention according to claim 2 is a method for forming a boron-containing semiconductor layer as described above, by implanting boron ions into a semiconductor layer that is thicker than a desired thickness, and then making the semiconductor layer have a desired thickness. This makes it possible to form a thin boron-containing semiconductor layer.

[Conventional technology]

Boron is a typical p-type impurity, and p-channel MO
Formation of source/drain regions of 3I-transistor, p
It is used to reduce the contact resistance of the semiconductor layer that contacts the mold head region.

On the other hand, there are various methods for incorporating impurities into a semiconductor layer, etc., but the ion implantation method is superior in that the total amount of impurities can be measured accurately and online.

[Problem to be solved by the invention]

However, in thin film transistors, thin film resistors, etc., the thickness of the semiconductor layer is thin. For example, the thickness of a Si layer for forming a thin film transistor is about 500 layers or less.

In such a thin semiconductor layer, the sheet resistance is high, so in order to reduce this sheet resistance, at least 2 to 5
It is necessary to contain impurities of the order of "X 101Sco+-".

However, in such a high-dose ion implantation apparatus, it is difficult to reduce the implantation energy to about 15 keV or less.

On the other hand, boron has a small mass number of lO, so compared to a substance with a large mass number, the projected range is longer even if the implantation energy is the same.

Therefore, it is difficult to implant boron ions so that the projected range is about half the thickness of a thin semiconductor layer, and it is difficult to form a thin boron-containing semiconductor layer by ion implantation.

[Means for Solving the Problems] A method for forming a boron-containing semiconductor layer according to claim 1 includes forming an insulating film 13 on a semiconductor layer 12 and introducing boron 15 into the semiconductor layer 12 through this insulating film 13. I'm trying to do ion implantation.

In the method for forming a boron-containing semiconductor layer according to a second aspect of the present invention, boron 15 is ion-implanted into the semiconductor layer 12 which is thicker than a desired thickness, and then the semiconductor J112 is made to have the desired thickness.

[Effect]

In the method for forming a boron-containing semiconductor layer according to claim 1, while the boron ions 15 pass through the insulating film 13, the implanted energy is absorbed by the insulating film 13, and since boron 15 has a small mass number, There are also fewer knock-on effects.

In the method for forming a boron-containing semiconductor layer according to the second aspect, since the semiconductor layer 12 is thicker than a desired thickness at the time of ion implantation of the boron 15, the implantation energy of the boron 15 is easily absorbed by the semiconductor layer 12 itself.

〔Example〕

Hereinafter, first and second embodiments of the present invention applied to the manufacture of a p-channel thin film transistor will be described with reference to FIGS. 1 to 3.

FIG. 1 shows a first embodiment. In this first embodiment, as shown in FIG. 1A, an St layer 12 with a thickness of about 400 layers is patterned on a SiO□ substrate 11 in the pattern of an active region of a thin film transistor, and a layer of St layer 12 with a thickness of about 50 nm is formed on a SiO□ substrate 11 to form a gate insulating film.
A 5i02 film 13 of about 0.0000000000000000000000000000000000000000000000000000000000000000000000000000000min0 quality type 5i02 type format type style shape form type form form is to form a 5i02 film 13 is deposited is 5i02 film 13 of approximately 0.000000000000000000000000000 type, type 5i02 film 13 is deposited, and St layer 14 is further patterned in the pattern of the gate electrode.

In this state, B15 ions are implanted.

Then, while +15 passes through the Sing film 13 on this day, the implanted energy is absorbed by the SiO□ film 13.

Therefore, even if an ion implanter with high implantation energy is used to implant ions at a high dose, B''15 can be implanted into a position approximately half the thickness of 5iN12.

Moreover, since B'15 has a small mass number, O in the SiO□ film 13 is knocked on by B'''15 and becomes 3
The knock-on effect of being injected into the fourth layer 12 is small.

However, on the other hand, because the mass number of B゛15 is small, B
Even if 15 is ion-implanted into the St layer 12, this 5
iJi12 is not completely amorphized. Therefore, crystallization does not proceed sufficiently in 5iJii12 even with subsequent annealing, and the sheet resistance of the Si layer 12 is large due to the small crystal grain size.

In such a case, it is known to temporarily make the Si layer 12 amorphous by implanting ions of an electrically inactive element such as Si (for example, in Japanese Patent Laid-Open No. 11907-1983).
Publication No. 9).

However, if Sjl is ion-implanted in the state shown in FIG. 1A after ion-implanting B''15, Si.

Since the mass number of is as large as 28, ○ in the Sing film 13
is knocked on by Si' and injected into the Si layer 12.

Therefore, in this first embodiment, as shown in FIG. 1B, Si
The Sing film 13 is patterned using the layer 14 as a mask, that is, the portions of the 34 layers 12 that are to be the source/drain regions of the thin film transistor are exposed, and in this state, the Sing film 13 is patterned.
i''16 ions are implanted.

Since Si''' 16 has a large mass number, even if an ion implantation device with high implantation energy is used and ion implantation is performed with the 34 layer 12 exposed, Si''' 16 will not be absorbed into the 5iJi 12.
16 can be efficiently implanted to completely amorphize this 34 layer 12.

In the p-channel thin film transistor manufactured in the first embodiment as described above, since Bo 15 is efficiently implanted,
The sheet resistance of the 34 layer 12 is low.

Moreover, by ion implantation of Si゛16, 5iJi1
Since 2 is once completely amorphous, crystallization progresses sufficiently by subsequent annealing, and since there is no knock-on by Si 16, no ○ is injected into the Si layer 12, and furthermore, this 0 makes it difficult to anneal. The crystallization of the 34 layer 12 at this time is not hindered. Therefore, the sheet resistance of 5jli12 is low due to these factors as well.

Furthermore, since 0 is not injected into 5iJilZ, 34
Junction leakage current in layer 12 is also low.

In the first embodiment described above, Si'16 was ion-implanted after the Bo 15 ion implantation, but Si'16 was first ion-implanted in the state shown in FIG. 1B, and then a 5i02 film was deposited, and then the Bo 15 may be ion-implanted.

In this case, with the deposited Si0g film remaining,
Next steps such as an annealing step can be performed.

Further, in the first embodiment described above, the St layer 14 for the gate electrode
Although the 34 layer 12 for the active region is formed above the 34 layer 12 for the active region, the 34 layer 12 for the active region may be formed above the Si layer 14 for the gate electrode.

By the way, instead of Bo 15, the large mass number F2°
If ion implantation is performed with the 34th layer 12 exposed, B can be implanted into a position approximately half the thickness of the 34th layer 12.

However, since F is also ion-implanted at the same time, crystallization of the 34-layer 12 by annealing is hindered, and the sheet resistance of the 34-layer 12 cannot be lowered.

FIG. 2 shows a second embodiment. In this second embodiment, as shown in FIG. 2A, a Si layer 14 for a gate electrode is patterned on a SiO□ substrate 11, a Si film 13 for a gate insulating film is deposited, and a Si layer 14 for an active region is further deposited. 34 layers 12 are deposited to a thickness of about 800 layers.

In this state, Bo 15 is ion-implanted to form source/drain regions, and Si'' is further ion-implanted in the same manner as in the first embodiment to make the 34 layer 12 amorphous.

In this case, since the thickness of the Si layer 12 itself is thicker than in the first embodiment, the implantation energy of B915 is easily absorbed by the Si layer 12 itself. Therefore, B.

15 is effectively implanted into 34 layers 12.

After that, in order to crystallize the amorphous 34 layer 12, 6
Pre-annealing is performed at a relatively low temperature of about 00° C. and annealing is performed at a higher temperature.

FIG. 3 shows the rate of crystallization during low temperature pre-annealing. As is clear from FIG. 3, in this second embodiment where the thickness of the 34 layers 12 is approximately 800 people, the thickness is 40
The time required for low-temperature pre-annealing may be shorter than when there are approximately 0 people involved.

Next, as shown in Figure 2B, RIE and N11l +11
The St layer 12 is etched by wet etching using 20□+11□0 or the like to a thickness of about 400 mm.

After this, normal steps such as formation of a glabellar insulating film, vapor deposition of Al, and formation of a vancivation film are performed.

In this second embodiment, 5iN12 for the active region is formed above the Si layer 14 for the gate electrode.
On the contrary, the 34 layers 12 for the active region may be formed first, and after the steps from ion implantation of Bo 15 to etching are performed on the 34 layers 12, the Si layer 14 for the gate electrode may be formed.

Furthermore, although the invention of the present application is applied to the manufacture of a p-channel thin film transistor in both the first and second embodiments described above, the invention of the present application can also be applied to the formation of a thin film resistor by ion-implanting B into the contact portion. can be applied.

〔Effect of the invention〕

In the method for forming a boron-containing semiconductor layer according to the first aspect, since the implantation energy of boron ions is absorbed by the insulating film while the boron ions pass through the insulating film, a thin boron-containing semiconductor layer can be formed.

Furthermore, since boron has a small mass number and has little knock-on effect on the insulating film, it is possible to form a boron-containing semiconductor layer whose characteristics are less affected by the insulating film.

In the method for forming a boron-containing semiconductor layer according to the second aspect, since the boron implantation energy is easily absorbed by the semiconductor layer itself, a thin boron-containing semiconductor layer can be formed.

[Brief explanation of drawings]

1 and 2 are side sectional views sequentially showing first and second embodiments of the present invention, respectively, and FIG. 3 is a graph of crystallization rate. In addition, in the symbols used in the drawings, 12-...-11------------5i layer 13-
・−−−−−・−・・−3iO□ film 15−−−−−・−
------・----B''.

Claims (1)

[Scope of Claims] 1. A method for forming a boron-containing semiconductor layer, in which an insulating film is formed on a semiconductor layer, and boron ions are implanted into the semiconductor layer through the insulating film. 2. A method for forming a boron-containing semiconductor layer, which includes implanting boron ions into a semiconductor layer that is thicker than a desired thickness, and then making the semiconductor layer have the desired thickness.