JPH02279048A - Fsk receiver - Google Patents

Abstract

PURPOSE:To lighten the weight and to eliminate the need for replacement of a crystal vibrator for each setting frequency by using an orthogonal detection reception system not requiring a high frequency filter set for each frequency band and a PLL local oscillation circuit. CONSTITUTION:The orthogonal detection reception system is adopted and a Phase Locked Loop(PLL) able to handle a crystal vibrator of many line frequencies is used for a local oscillator of a selective call receiver. When the orthogonal detection reception system is adopted in this way, small size and light weight are attained because of no high frequency filter required. Moreover, when the PLL oscillation circuit is in use, an optional frequency is set. Thus, replacement of the crystal vibrator for each setting frequency is not required and stock and maintenance parts are reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on PLL (Phase Locked L).
oop) oscillation circuit and AFC (Auto+atic
The present invention relates to an FSX receiver using an orthogonal detection method using a frequency control circuit.

(Prior art) In recent years, advances in integrated circuit technology have led to the miniaturization of receivers. However, taking the radio section as an example, since the basic circuit system is the same, integration is either impossible or impossible. At present, we are approaching the limit of miniaturization due to the existence of difficult elements.

For example, in a superhetero gain receiver, high frequency, intermediate frequency filters, etc. require a large area.

Therefore, an orthogonal detection reception method has been considered in order to reduce the size and weight.

The quadrature detection reception method equalizes the line frequency and local oscillation frequency, uses a mixer to extract the beats of the reception frequency and local oscillation frequency, uses a low-pass filter to generate only the baseband signal, and limits the amplitude of this beat using a limiter circuit. After that, demodulation processing is performed to obtain a demodulated signal.

This orthogonal detection reception system is characterized in that the local oscillation frequency and line rewave number match, so the intermediate frequency is zero and there is no image frequency. This means that highly selective filters for attenuating the image frequency are not required in the high frequency amplifier and intermediate frequency amplifier.

Furthermore, since the channel filter for attenuating adjacent channel interference waves has an intermediate frequency of zero, it can be configured with a low-frequency active filter and can be realized on an integrated circuit.

Furthermore, by using AFC technology in the orthogonal detection receiving method, the problem of the conventional sensitivity band characteristics being narrow can be solved, and sensitivity band characteristics equivalent to those of the superhetero gain method can be obtained.

[Problem to be solved by the invention]

As described above, by employing the orthogonal detection reception method in the receiver, it becomes possible to eliminate the high frequency filter and the intermediate frequency filter, and the receiver can be made smaller and lighter. Further, since a high frequency filter or the like is not required, there is no need to change the high frequency filter for each frequency, which was necessary in the single superheteron system.

However, in this type of receiver, it is still necessary to change the local oscillation frequency in accordance with the line frequency. In particular, since it is necessary to change the crystal resonator for each frequency, there are problems in that the specifications for manufacturing become complicated, the number of stock and maintenance parts increases, and the manufacturing cost increases.

An object of the present invention is to provide an FSK receiver that is smaller in size and lighter in weight, and also has simplified specifications and a reduction in stock and maintenance parts.

[Means to solve the problem]

The present invention uses an orthogonal detection reception method and uses a PLL capable of handling multiple line frequencies with a single crystal oscillator as a local oscillator of a selective call receiver.

That is, the FSK receiver of the present invention includes a PLL oscillation circuit that includes at least a reference oscillator as a local oscillation signal, and a PLL oscillation circuit that includes at least a reference oscillator as a local oscillation signal.
a mixer circuit that generates a baseband signal using the same local oscillation frequency as the line frequency output from the L oscillation circuit; a quadrature detection demodulation circuit that obtains a demodulated signal from this baseband signal; and an AFC circuit that controls the PLL oscillation circuit based on the PLL oscillation circuit.

This AFC circuit includes a demodulation circuit that outputs a frequency detection signal of the baseband signal, an average value circuit that outputs an average value voltage of the signal output from this demodulation circuit, and an offset voltage that is superimposed on this average value voltage. offset circuit,
It has a comparator circuit that compares the signal output from the demodulation circuit with the signal output from the offset circuit and outputs a stop signal, and a waveform signal oscillation circuit that has a function of holding the output voltage using the stop signal.

The reference oscillator of the PLL oscillation circuit is constituted by a voltage controlled oscillation circuit, and the control voltage of this voltage controlled oscillation circuit is used as the output voltage of the waveform signal oscillation circuit.

[Effect]

In this configuration, by using the orthogonal detection reception method,
Since it does not require a high frequency filter, it can be made smaller and lighter. In addition, by using a PLL oscillation circuit,
It is possible to set any frequency, and there is no need to replace the crystal oscillator for each set frequency, making it possible to reduce stock and maintenance parts.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, received waves frequency-modulated with binary digital signals of marks or spaces are amplified by a high frequency amplifier l and input to mixer circuits 2, respectively.

In addition, the local oscillation signal generated by the PLL oscillation circuit 9 is 9
The signals are input to the 0 degree phase shifter 8, and the phase thereof is +45 degrees.

The angle is changed by -45 degrees and input to the mixer circuit 2.

In this mixer circuit 2, signals with a phase shift of 90 degrees are frequency-converted to baseband and output.

Since the line frequency and local oscillation frequency match, this baseband signal becomes the beat frequency. Then, only the baseband signal is extracted by the low-pass filter 3, and the noise band is limited.

Furthermore, the baseband signals are input to a limiter circuit 4, respectively, and binarized signals 1. Get Q. And these signals 1. Q is input to the demodulation circuit 5, where frequency detection is performed.

As shown in FIG. 2, the demodulation circuit 5 is constituted by a D flip-flop, and a signal 1 is inputted to its clock input CL, and a signal Q is inputted to its data output. As a result, as shown in each signal waveform in FIG. 3, when data is counted at the rising edge of the clock, an output signal is obtained. From now on, signal 1. It can be seen that by changing the phase of Q by 90 degrees, the output also changes in the same way and the data is demodulated.

The signal demodulated in this manner has noise removed by a low-pass filter 6, is further binarized by a comparator 7, and is output as a binary digital signal.

Moreover, the signal 1. Q, here the signal Q is AFC
input to the circuit 10, and this AFC circuit IO causes the PL
It controls the L oscillation circuit 9.

The details will be described later.

An example of the PLL oscillation circuit 9 is shown in FIG.

As shown in the figure, the PLL oscillation circuit 9 includes a variable frequency divider 11,
Reference oscillator 122 Phase comparator 13. Low pass filter 1
4. Voltage controlled oscillator (VCO)
trolled 0scillator) 15,
PLL control circuit 16. and frequency specification ROM
(Read 0nly Mewary) Consists of 17.

The oscillation frequency of the voltage controlled oscillator 15 is divided by the variable frequency divider 11, the phase difference between the output signals of the variable frequency divider 11 and the reference oscillator 12 is compared by the phase comparator 13, and the error signal is converted into a low-frequency signal. An error voltage is obtained by passing it through a pass filter 14. The oscillation frequency is controlled by using this error voltage as the control voltage of the voltage controlled oscillator 15, and the oscillation frequency is maintained at a constant value for this error signal.

Note that the PLLt# control circuit 16 reads the frequency designation signal S from the frequency designation ROM 17, and outputs the frequency designation signal obtained based on this to the variable frequency divider 11, thereby controlling the frequency division of the variable frequency divider 11. Change the circumferential ratio.

Therefore, the PLL oscillation circuit 9 can obtain an oscillation frequency corresponding to this frequency designation signal.

Further, in this example, the reference oscillator 12 is a voltage controlled crystal oscillator (VCXO: Voltage Control
ed X'talOscillator). The control signal for this voltage crystal oscillator is an output signal from the AFC circuit 10, and the frequency of the reference oscillator 12 is linearly changed by the voltage change of this output signal. Therefore, due to this change in the reference oscillation frequency, the oscillation frequency of the voltage controlled oscillator 15 is also linearly changed.

Note that the oscillation frequency of the reference oscillator 12 is l0KH.

Assuming that the number of bits of the frequency designation signal S is 14 bits, the maximum set frequency of this PLL oscillation circuit 9 is (2Isl) x 10 KHz "327.67
MHz.

The AFC circuit 10 includes the limiter circuit 4 shown in FIG.
Detects the offset frequency with respect to the line frequency by frequency detecting the output signal Q of , and when the offset frequency becomes within a certain value, stops the reference oscillator 12 of the free-running PLL oscillation circuit 9 at a certain frequency, The oscillation frequency of the PLL oscillation circuit 9 is made to follow the line frequency.

As shown in FIG. 5, this AFC circuit 10 includes a demodulation circuit 18. Low pass filter 19. Average value circuit 20. Offset circuit 21. Comparator circuit 22.23. AND circuit 24. It is composed of a sawtooth wave generation circuit 25.

The demodulation circuit 18 is configured as a delay detection circuit including a delay circuit 26 with a delay time T and an exclusive OR circuit 27, as shown in FIG.

As shown in FIG. 7, the low-pass filter 11 includes an operational amplifier 28. Resistance 29, 30. It consists of capacitors 31 and 32.

As shown in FIG. 8, the average value circuit 20 is composed of a primary RC integrating circuit consisting of a resistor 33 and a capacitor 34.

The offset circuit 21 includes a voltage follower 35° resistor 3
6,37. It is composed of constant current circuits 38 and 39.

Comparator circuits 22, 23 include transistors 40, 41 . Resistance 42.43. A differential amplifier consisting of a constant current circuit 44 and a transistor 45. It consists of a level shifter consisting of a resistor 46.

Furthermore, the sawtooth wave generating circuit 25 has R as shown in FIG.
S latch 47. Comparator 48, 49° constant current circuit 5
2-53. Resistors 54, 55. Capacitor 56. It is composed of a switch 57.

The operation of this AFC circuit 10 will be explained using the waveform diagram of FIG.

In FIG. 11, it is assumed that the signal Q is the output of the limiter circuit 4 and is applied with an offset frequency ΔF. That is, in a mark or space, the frequency of signal Q is ±FD-ΔF.

The output of the demodulation circuit 18 becomes a pulse wave with a pulse width T indicated by D. By integrating D with a low-pass filter 19, a voltage output O proportional to the frequency of the signal Q is obtained.

The average value of O becomes the voltage output of the FD, which is independent of ΔF. This is because the frequencies of signal Q are FD-ΔF and 1-FD
-ΔF1, so the frequency average value is FD.

To obtain the average value A of the signal 0, the 0 time constant used by the average value circuit 20 is set to be sufficiently longer than 1/BR.

Next, the average value A is input to the offset circuit 21 and ±ΔV
The voltages V, , VL are obtained.

VW = A + AV, VL = A - In the AV offset circuit 21, the average value A passes through the voltage follower 35 and generates an offset voltage ΔV by the resistor 36.37 and the constant current circuit 38.39.

The comparator circuits 22 and 23 each have Vol.
, VOL is input. Comparator circuit 22゜2
3 is due to the action of the differential amplifier and level shift, respectively.

When O>v, VOL becomes H”, and VOL becomes 0<VOL.
It is set so that it becomes H" when

These V. H2vOL is input to the AND circuit 24, and ■
. , VOt are both "H", the output C of the AND circuit 24 becomes "H". This means that the signal 0 is equal to the average value A.
This shows that the signal C becomes H'' when the value is within 67 from .

If the demodulation sensitivity in one day of the demodulation circuit is KD (V/KHz), which shows this in concrete numerical value, the signal 0 becomes 0-KD・ΔF, and when ΔF>KD・ΔF, the signal becomes “H”. Become.

If KD=10mV/KHz and ΔV=10mV, when ΔF<IKHz, signal C becomes HII.

The sawtooth wave generation circuit 25 uses an RS latch 47 and comparators 4B and 49, charges a capacitor 56 with a constant current circuit 50, and when the voltage reaches the high voltage side set voltage VCN or higher, the RS latch 47 is inverted, and the constant current circuit 51 charges the capacitor 56. The zero-order, low voltage side setting voltage V that rapidly discharges the capacitor 56
When the voltage becomes lower than Ct, the RS latch 47 is reversed and the constant current circuit 50 starts charging again. By repeating this, a sawtooth wave is generated.

The sawtooth wave generating circuit 25 is a circuit that stops free running when the signal C is "H" and maintains the voltage vT at that time. When the signal C becomes "H", the constant current circuit 50.51
is turned off and enters a high impedance state.

The output v7 of the sawtooth wave generation circuit 25 is input to the reference oscillator 12 of the PLL oscillation circuit 9. Therefore, the voltage controlled oscillator 15 is operated by the sawtooth wave generating circuit 25 at the 13th
It will run on its own at the cycle shown in the figure. Here, 1
In order for the period to fall within one bit, the period of the sawtooth wave must be shorter than the data transmission rate. Furthermore, as shown in FIG. 13, the local oscillation frequency needs to change above and below the line frequency.

This is because it is impossible to determine whether the beat frequency input to the AFC circuit has a frequency offset applied to the positive side or the negative side, so the local oscillation frequency is adjusted above and below the line frequency. This is because it is necessary to detect a point at which the offset becomes small by changing the offset.

By periodically changing the local oscillation frequency, the baseband signal 1. Q changes similarly. Therefore, since there is always one time in one bit when the error between the line frequency and the local oscillation frequency falls within a predetermined frequency, the signal C also becomes H'' at least once in one pit. At this point, since the output (7) of the sawtooth wave generation circuit becomes a constant value, the local oscillation frequency becomes within a predetermined frequency range of the line frequency, and it is understood that AFC is applied.

From the above, a PLL oscillation circuit is used as a local oscillation circuit in a quadrature detection reception method using an AFC circuit, the reference oscillator is a voltage-controlled crystal oscillator, and the output of the AFC circuit is a voltage-controlled B
This is used as the control voltage for the crystal oscillator. This is completely equivalent to applying AFC to a fixed frequency local oscillation circuit.

〔Effect of the invention〕

As explained above, the present invention provides an orthogonal detection reception method that does not require high-frequency filters set for each frequency band, and a PL
By using an L local oscillation circuit, there is no need for a high frequency filter, making it more compact.

It is possible to reduce weight, and since it is possible to set any frequency, there is no need to replace the crystal oscillator for each set frequency, reducing stock and maintenance parts.

This has an extremely large effect on reducing manufacturing costs by unifying manufacturing specifications.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the overall configuration of the FSK receiver of the present invention, Figure 2 is a circuit diagram of the demodulation circuit, Figure 3 is a waveform diagram of input and output signals of the demodulation circuit in Figure 2, and Figure 4 is A block diagram of the PLL oscillation circuit, Figure 5 is a block diagram of the AFC circuit, and Figure 6 is a block diagram of the AFC circuit.
Figure 7 is a circuit diagram of the demodulation circuit, Figure 7 is a circuit diagram of a low-pass filter, Figure 8 is a circuit diagram of an average value circuit, Figure 9 is a circuit diagram of an offset circuit, and Figure 10 is a circuit diagram of a comparator circuit. , FIG. 11 is a circuit diagram of the sawtooth wave generation circuit, FIG. 12 is a diagram showing signal waveforms of each part in the AFC circuit, and FIG. 13 is a diagram showing signal waveforms of each part of the sawtooth wave generation circuit. DESCRIPTION OF SYMBOLS 1...High frequency amplifier, 2...Mixer, 3...Low pass filter, 4...Limiter circuit, 5...Demodulation circuit, 6...Low pass filter, 7...Comparator , 8... 90 degree phase shifter, 9... PLL oscillation circuit, I
O...AFC circuit, 11...Variable frequency divider, 12...
・Reference oscillator (VCXO), 13...phase comparator, 1
4...Low pass filter, 15...Voltage controlled oscillator (VCO), 16...PLL control circuit, 17...Frequency specification ROM, 18...Demodulation circuit, 19...Low pass Filter, 20... Average value circuit, 21... Offset circuit, 22.23... Comparator circuit, 24
...AND circuit, 25...Sawtooth wave generation circuit. Fig. 4 Fig. 3 Fig. 3 Severe stop- Fig. 6 Fig. 10 Fig. 12 Fig. 13 (V)

Claims (1)

[Claims] In an FSK receiver that receives a modulated wave frequency-modulated with a 1- or 2-value digital signal, a PLL oscillation circuit that includes at least a reference oscillator as a local oscillation signal, and a local oscillation circuit that has the same line frequency as the line frequency output from this PLL oscillation circuit. a mixer circuit that generates a baseband signal using frequency;
a quadrature detection demodulation circuit that obtains a demodulated signal from this baseband signal;
and an AFC circuit that controls the L oscillation circuit.
The circuit includes a demodulation circuit that outputs a frequency detection signal of the baseband signal, an average value circuit that outputs an average value voltage of the signal output from this demodulation circuit, and an offset circuit that superimposes an offset voltage on this average value voltage. a comparator circuit that compares the signal output from the demodulation circuit with the signal output from the first offset circuit and outputs a stop signal; and a waveform signal oscillation circuit that has a function of holding the output voltage using the stop signal. An FSK receiver comprising: a reference oscillator of the PLL oscillation circuit formed of a voltage controlled oscillation circuit, and a control voltage of the voltage controlled oscillation circuit being the output voltage of the waveform signal oscillation circuit.