JPH02278867A - Complementary mos field effect transistor - Google Patents

Abstract

PURPOSE:To suppress extension of a depleted layer and to reduce deterioration of an element due to a short channel effect by employing a P<+> type polysilicon as the material of a gate electrode on a P-channel MOSFET forming region. CONSTITUTION:An oxide film 2 is formed on a conductivity type silicon substrate 1 by thermal oxidation, and a reverse conductivity type well 5 to the conductivity type is formed in the substrate 1. A field oxide film 6 is formed on the substrate to isolate an element, and a gate oxide film 7 and a nondoped polysilicon 8 are sequentially formed thereon. Then, P-type impurity ions are implanted to the polysilicon 8 to form a P<+> type polysilicon 10, and patterned by a lithography step to form a gate electrode 11 of the P<+> type polysilicon. Thereafter, a first source region 15 and a first drain region 16 are formed in an N-channel MOSFET forming region 14. On the other hand, a second source region 18 and a second drain region 19 are formed in a P-channel MOSFET forming region 12. Thus, a complementary MOS field effect transistor having excellent hot carrier resistance is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a complementary MOS field effect transistor (hereinafter abbreviated as CMOSFET).

(Uc coming technology) UC coming n channel MOSFET and n channel MOSF
CMOSFE where ETs are made on the same substrate and used in a complementary manner by combining them.
T is a very important technology for realizing low power consumption LSI.

+ Figure 2 shows a dignified n gate electrode (n+ polysilicon)
A cross-sectional view of the structure of the CMO9FET is shown.

A p-type region (this is called a p-well) is formed on the n-type substrate 21.

) is provided on the n-type substrate 21, and a p-channel MOSF
ET is formed, and n-channel MO3 is formed on the p-well 22.
FE'T' is formed.

The gate electrodes 23 used here are both made of n+ polysilicon, usually non-doped polysilicon, formed by chemical vapor deposition (CVD), and then phosphorus ions (P), which is an n-type impurity, are diffused. Form.

By using n-polysilicon as the gate electrode 23, the n-channel MOSFET is a surface channel type, p-channel iV
The IOS FET is a buried channel type.

(Problem to be solved by the invention) However, in the conventional CMOSFET mentioned above, the LS
As the degree of integration of I increases and the miniaturization of elements progresses, deterioration of the elements due to the short channel effect has become a problem, and countermeasures are urgently needed.

Conventionally, as a MOSFET, an n-channel MOSFET 'I' having a gate electrode of n+ polysilicon has been widely used. The reason why the gate electrode is made of n+ polysilicon is that the threshold voltage can be easily controlled and the manufacturing process is stable.

Even after p-channel MOSFETs began to be widely used, n+ polysilicon was used for the gate electrode as in n-channel MOSFETs9.
Regarding T, it is necessary to form a p layer under the gate electrode in order to control the threshold voltage, and it is a buried channel type.

However, the p-channel MOSFET is
In addition to the fact that the junction depth of the source and drain cannot be physically reduced compared to SFET, buried channel type
■The position of the formed channel is far from the gate electrode, and the influence of the gate voltage is small. ■The junction of the channel part from Sonis to the drain is p+-p-r)+
This causes a short channel effect, such as an increase in the influence of the drain voltage on a diagonal channel where no pn junction exists, and there is a limit to miniaturization.

An object of the present invention has been made in view of the above-mentioned conventional problems, and is to provide a CMOSFET in which the deterioration of the device due to the short channel effect is reduced.

(Means for solving the three problems) In order to achieve this purpose, the CMOSF E of this invention
T is an oxide film formed by thermal oxidation on a conductivity type silicon substrate, a well of an opposite conductivity type to the conductivity type formed in the 11n substrate, and a well formed on the substrate for element isolation. A field oxide film, a gate oxide film and non-doped polysilicon sequentially formed on the field oxide film, and p-silicon for the non-doped polysilicon.
type impurity ions are implanted, and the unformed p-polysilicon is buttered by a phosphorography process, forming a gate electrode of the p+ polysilicon and a gate electrode formed in the n-channel MOSFET formation region. a first source region and a first drain region, a second source region and a second drain region formed in the p-channel MOSFET formation region, an insulating film and an At interconnection formed sequentially on the substrate. It is characterized by having the following.

(Function) According to the CMOS FET of the present invention, by using p+ polysilicon as the material of the gate electrode in the p-channel MOSFET formation region, there is no need to use a buried type to form a p layer under the gate electrode. This makes it possible to suppress the spread of the depletion layer. Therefore, the problem of short channel effect can be avoided, and the amount of hot carriers generated can be reduced.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the drawings referred to in the following examples are merely schematic illustrations to facilitate understanding of the present invention.
It should be understood that this invention is not limited only to these illustrated examples (Explanation of manufacturing process) Figures 1 (a) to (i) are cross-sectional steps of CMOSFET for detailed explanation of this invention. It is a diagram.

First, 5i02J was deposited on a p-type silicon substrate 1 by thermal oxidation.
After about 7,000 layers of lsI2 are grown over the entire surface, a resist batten 3 with no holes is formed only in the well formation region 4 by a lithography process. Use resist 3 as a mask
ζ The 5i02 film 2 in the well forming region 4 is removed by etching. (See FIG. 1(a)) Furthermore, in the state of FIG. 1(a), using the 5i02 film 2 as a mask, phosphorus ions (P), which is an n-type impurity, are applied at an acceleration voltage of 170 keV and a dose of 1.6E] for 3 m Ion implantation is performed at -2. After removing the resist 3 by etching, ions are implanted and phosphorus ions are thermally diffused to form an n-type well 5. Well diffusion was carried out in a nitrogen atmosphere for 360 minutes, approximately 1
The temperature is 150° C., and the diffusion depth is about 4.0)t, m. (See FIG. 1(b)) Thereafter, the 5i02 film 2 formed on the entire surface is removed by etching.Then, a field oxide film 6 for element isolation is formed. First, a thin Si3N4 film (not shown) is formed in advance in the area outside the field oxide film 6 forming area, and then the field oxide film 6 is heated by thermal oxidation to approximately cpoo.
Form into o.

(See FIG. 1(c)) Next, gate oxide M, 7 is formed, and non-doped polysilicon 8 of about 3500 Å is formed thereon.

Furthermore, polysilicon oxidizes JB by thermal oxidation! form 9. (See Figure 1(d)) Then, in the state shown in Figure 1(ci), boron ions (BF2), which are p-type impurities, are implanted at an accelerating voltage of 70 keV, a dose of H1, and an OE of 15 cm-2. Polysilicon 10 is formed. In this process,
The polysilicon oxide film 9 serves to prevent boron ions from penetrating into the substrate 1 during ion implantation. (See FIG. 1(e)) Then, by a phosphorography process, p polysilicon 1
0 and p polysilicon gate electrode 1
1 (hereinafter abbreviated as p gate electrode).

) to form. (See Fig. 1(f)) In the state shown in Fig. 1(f), thermal oxidation was performed at a low temperature of 850°C to form an oxide film (5° OA on the p-gate electrode 11 and 200 AL:r) on the other surfaces. (not shown) is formed, and then a p-channel inter-O3FET formation region 12 is formed.
A resist 13 is formed on the well formation region 4.

After that, using the p+ gate electrode 11 as a mask, the n-channel M
Arsenic ions (As+), which are n-type impurities, are implanted into the OS FX E T forming region 1411Tl to form a source region 15 and a drain region 16. Note that the impurity concentration of n in the source and drain regions is approximately 2.0E20□-
The ion implantation conditions are set so that 3. In this step, the p+ gate electrode (box 1
The oxide film on 1 is Jl! ! Since it has a thickness of 50 OA, it functions as an implantation prevention film during ion implantation (see FIG. 1(g)).Furthermore, the same process as the process in FIG. 1(g>) is used.

First, the n-channel MOSFET formation region 14 is covered with a resist 17. Next, using the p+ gate electrode 11 as a mask, a p
Boron ions, which are p-type impurities, are ion-implanted into the interchannel O3FET formation region 12, and the source region 1 is
8 and a drain region 19 are formed. Note that the p-type impurity concentration in the source and drain regions is approximately 7.0 E 19 cm.
The ion implantation conditions are set so that -3. In addition, p
The function of the oxide film on the gate electrode 11 is the same as described above.

(See FIG. 1(h)) Thereafter, the polysilicon oxide film 9 formed on the resist 17 and the p-gate electrode 11 is removed by etching. Then, the insulating film 20 and the A1 wiring 21 are sequentially formed, and the process of forming the p' gate electrode CMOSFET is completed. (Figure 1(i)
(Reference) (Description of comparative experiment) Here, we conducted an acceleration experiment of the CMOSFET with a p gate ring ff (p+ polysilicon) of this invention and the conventional CMOSFET with an n gate electrode (l polysilicon), and compared the transistor life. I went and tried it.

The conventional It2 gate electrode and electrode CMO8FET had the structure shown in FIG. 2.

The experimental conditions are explained below.

■Test 1 is a p+ gate electrode (
p+ polysilicon) and n gate ring fa
t (n+ polysilicon).

A total of four types of samples are prepared: one in which a p gate electrode is formed on an n-channel MOSFET and one in which an n+ gate electrode is formed.

■The applied voltage is 6V for the drain voltage for n-channel type,
The gate voltage is 3V; l) For the channel, the drain voltage is -8V and the gate voltage is -2V.

(2) The experiment involved continuous application of voltage to the four types of samples mentioned above. Under such operating conditions, the time elapsed for the mutual conductance gm to fluctuate by a value equivalent to 10% of the initial value is defined as the lifetime of the transistor,
Measures the lifetime of the transistor against the gate length.

3 and 4 are graphs of transistor life versus gate length.

As a result of implementation, Figure 3 shows an n-channel MOSFET (
Curve A shows the one in which a Cp gate electrode is formed, and n
Curve B does not show the gate ring □□□. Comparing curve A and curve B, looking at the lifespan of a transistor when the gate length is 1°0 μm, curve B is approximately 500 seconds, curve A is approximately 500 seconds.
is approximately 10,000 seconds. Therefore, p-channel M
By forming a p+ gate electrode in O3FE'l', the lifetime of the transistor is extended.

In Figure 4, curve C shows an n-channel MOSFET with a p+ gate electrode formed thereon, and curve C shows an n-channel MOSFET with an n+ gate electrode formed thereon. Looking at the lifespan of a transistor, the curve lasts about 200 seconds.

Curve C is about 3000 seconds. 6'e, n
By forming a p+ gate electrode in the channel MOSFET, the lifetime of the transistor is extended.

From the above experimental results, the lifetime of the transistor can be extended by forming p+ gate electrodes in both the n-channel MOSFET formation region and the n-channel MOSFET formation region in the CMO8FET.

Therefore, it can be confirmed that the CMOSFET of the present invention has less short channel effect and less hot carrier effect.

Note that in this example, an n-well was formed in an n-type silicon substrate, but it is also possible to form an n-well in an n-type silicon substrate, or to form both an n-well and 1) well in a low-concentration silicon substrate. A similar effect can also be expected. Alternatively, a polycide gate may be formed by forming a metal such as tungsten silicide on the gate electrode to reduce the gate resistance rM.

(Effect of the invention) As is clear from the above explanation, the CMO of this invention
In 3FIET, by changing the material of the gate electrode from It+ polysilicon to p-polysilicon, it is possible to avoid the short channel effect problem and create a complementary MO9O9 field effect transistor with excellent hot carrier resistance. can.

Therefore, the present invention can provide a semiconductor substrate f=integrated circuit device, particularly a highly integrated complementary MO3 field effect transistor.

[Brief explanation of drawings]

Figures 1 (a) to (i) are cross-sectional process diagrams of a CMOSFET for explaining the details of this invention, and Figure 2 is a CMOSFET with an n gate electrode (11+ polysilicon) as a conventional technology.
Structural sectional view of T. 3 and 4 are graphs of transistor life versus gate length. 1... 1) type silicon substrate 2... 5i02 film 5... [1 type well 6... Field oxide film 7... Gate oxide film 8... Non-doped polysilicon oxide film 9... Polysilicon oxide film 10・・p polysilicon+ 11・・p polysilicon gate electrode 15.18・・
Source area 16.19... Drain region 20... Insulating film 21 ・ Al wiring ↑ ↑ Applicant Oki Electric Industry Co., Ltd. 12 ・P~nel MOSFET mold 4 13.17...
・Register 1 or gate 14 = n-channel MOSFET ftl, kjl Kei 1
5. Old... So people (IN CMOSFET's? Button process diagram Figure 1 (T's 2) CMOSFET's m'al th'(T's 1) Figure 2 0.6 O7 B 1.0 Cate length [JJm] 1.3 long length 1z
Inside 4〉Diff @4 figure

Claims (1)

[Scope of Claims] An oxide film formed by thermal oxidation on a conductivity type silicon substrate; a well of an opposite conductivity type to the conductivity type formed in the substrate; and a well formed on the substrate for element isolation. p-type impurity ions are implanted into the field oxide film, the gate oxide film and non-doped polysilicon sequentially formed on the field oxide film, and the non-doped polysilicon. polysilicon, a p^+ polysilicon gate electrode formed by patterning the p^+ polysilicon by a lithography process, a first source region and a first drain formed in the n-channel MOSFET formation region; area and p-channel MOSF
A complementary MOS field effect transistor comprising a second source region and a second drain region formed in an ET formation region, an insulating film and an Al wiring sequentially formed on the substrate.