JPH02278836A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To prevent a defect due to damage by a plasma while an effect to enhance a characteristic of a TFT is being secured by a method wherein a semiconductor device whose channel region of an insulated-gate field-effect transistor is composed of a non-single-crystal semiconductor is exposed to a plasma atmosphere containing ammonia. CONSTITUTION:A non-single-crystal silicon thin film is deposited on an insulating amorphous material 1-1 ; after that, a thin film 1-2 is formed; a gate oxide film 1-4 is formed by a thermal oxidation method. By this oxidation process, a crystal growth operation of the thin film 1-2 progresses; this thin film is transformed into a polycrystalline silicon thin film 1-3. Then, a gate electrode 1-5 is formed; ions of an impurity element are implanted by making use of the gate electrode 1-5 as a mask; a source region 1-6 and a drain region 1-7 are formed. Then, an interlayer insulating film 1-8 is deposited; a heat treatment is executed; after that, a substrate is set in a reaction chamber; a gas containing hydrogen gas or ammonia gas is introduced. When high-frequency power is applied, a plasma is generated easily; a hydrogen radical is introduced into the substrate. Thereby, a high performance of a transistor can be realized without a defect due to damage by the plasma.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is produced using a non-single crystal semiconductor thin film formed on an amorphous insulating substrate or an insulating film such as an insulating transparent substrate. The present invention relates to thin film semiconductor devices such as thin film transistors and methods for manufacturing the same.

[Prior Art] A large number of dangling bonds exist in a non-single crystal semiconductor thin film such as amorphous silicon wIm or a polycrystalline silicon thin film. For example, in a polycrystalline silicon thin film, defects such as dangling bonds that exist at grain boundaries become trap levels for carriers and act as a barrier to carrier conduction (, (J, Y, W, 5et
o, J., Appl, Phys., 46
．． p5247 (1975)). Therefore, in order to improve the performance of polycrystalline silicon thin film transistors, it is necessary to reduce the defects. (J, App
l, Phys, 53 (2).

p1193 (1982)). For this purpose, the defects are terminated with hydrogen, and the main methods known include hydrogen plasma treatment, hydrogen ion implantation, and hydrogen diffusion from a plasma nitride film. .

The hydrogen ion implantation method has the disadvantage of requiring an expensive ion implanter, and the hydrogen diffusion method from the plasma nitride film deposits an unnecessary nitride film. It has its drawbacks. Therefore, the hydrogen plasma treatment method is the most excellent method. (T, 1.Kami
ns, IEEE Electron Device
Letters, Vol, EDL-1, No. 8. p1
59° (1980)).

Polycrystalline silicon ff1l) transistor ON current engineering. .

is expressed by the following formula.

IO+1 a: 1 − exp (−A −N
t”/kT)・・(1) In 22, 1 is the grain size, and Nt is the Tra existing at the grain boundary.
p density, k represents Boltzmann's constant, T represents temperature, and A represents proportionality constant. (J, Levinson, J, App
l, Phys, 53 (2), p1193, (19
82)) Reducing defects by performing the hydrogen plasma treatment means reducing Nt in equation (1).

[5! [5M that Akira is trying to solve] However, in conventional plasma processing using hydrogen gas, TP
There were many defects caused by plasma damage, such as a shift in Vth (L, threshold voltage) of T, and defects in gate withstand voltage, making it difficult to put it into practical use.

Therefore, the present invention secures the effect of improving TPT characteristics while
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that completely eliminates defects caused by the plasma damage described above.

[Means to solve the problem] The semiconductor device of the present invention has the following features.

(1) In a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the semiconductor device is immersed in a plasma atmosphere containing at least ammonia.

(2) In a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the semiconductor device is immersed in an asymmetric plasma atmosphere containing at least one of hydrogen and ammonia.

(3) In a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the semiconductor device is immersed in a plasma atmosphere containing at least one of hydrogen and ammonia. Heat treatment is performed in an atmosphere containing hydrogen.

Furthermore, the method for manufacturing a semiconductor device of the present invention has the following features.

(1) A method for manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, including at least the step of immersing the semiconductor device in a plasma atmosphere containing at least ammonia.

(2) In a method of manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the step of immersing the semiconductor device in a plasma atmosphere containing at least one of hydrogen and ammonia. , and the glasma is asymmetric.

(3) In a method of manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, a step of immersing the semiconductor device in a plasma atmosphere containing at least one of hydrogen or ammonia; It has at least a step of heat-treating in an atmosphere containing at least a little hydrogen.

〔Example〕

Embodiment 1 A first embodiment of the present invention will be explained according to the process diagram of a thin film transistor shown in FIG. In the same figure (a), a non-monocrystalline silicon thin film is formed on an insulating amorphous material 1-1 such as an insulating amorphous substrate such as glass or quartz or an insulating amorphous material layer such as 5i02. After that, a non-single crystal silicon N film 1-2 is formed by photolithography. As a method for forming the silicon thin film, there are the following methods. (1) Low pressure CVD method, MBE method (M.

Polycrystalline silicon is deposited using a method such as regular beam epitaxy).

(2) EB (Electron Beam) vapor deposition method,
An amorphous silicon thin film or a microcrystalline silicon thin film is deposited by a method such as a sputtering method, a plasma CVD method, a photoexcitation CVD method, a low pressure CVD method, or an MBE method. For example, in the low pressure CVD method, an amorphous silicon thin film can be deposited by setting the deposition temperature to about 550° C. or lower.

Next, as shown in FIG. 4B, a gate oxide l11-4 is formed by a thermal oxidation method. If the dry oxidation method is used, a high-quality gate oxide film with high breakdown voltage can be obtained by heat treatment at about 1150° C. in an oxygen atmosphere. If a wet oxidation method is used, an oxide film can be formed even at a low temperature of about 900° C., but the breakdown voltage is lower and the film quality is inferior to that of a film formed by a dry oxidation method. Through this oxidation process, the non-single crystal silicon thin film 1-2 progresses in crystal growth due to heat treatment, and becomes a polycrystalline silicon thin film 1-3. When a polycrystalline silicon thin film is used as the non-monocrystalline silicon thin film 1-2, the polycrystalline silicon thin film 1-2 after the oxidation step
The crystal grain size of No. 3 is about 2000A to 3000A. When an amorphous silicon thin film or a microcrystalline silicon thin film is used as the non-single crystal silicon thin film 1!1-2, the crystal grain size grows from 5000 to several μm.

Next, as shown in FIG. 5C, a gate electrode 51-5 is formed. Polycrystalline silicon is used in the gate electrode material. Subsequently, using the gate electrode 1-5 as a mask, impurity elements are ion-implanted to form a source region 1-6 and a drain region 1-7. Phosphorus, arsenic, boron, or the like is used as the impurity element.

Next, as shown in the same figure (d), the insulation between the eyebrows Jl! Deposit 1-8. Subsequently, impurity activation of the source region 1-6 and drain region 1-7 and interlayer insulation j1!1-
Heat treatment is performed at about 600°C to 1000°C for the purpose of densification in step 8. After that, plasma treatment is performed. 1-9 indicates highly active hydrogen radicals. Plasma processing can be performed using a normal plasma CVD apparatus. A substrate is set in a reaction chamber, and a gas containing at least one of hydrogen gas and ammonia gas is introduced into the reaction chamber. The internal pressure is approximately 1 to 3 Torr.

Plasma is easily generated by applying high frequency power of 13.56 MHz to the parallel plate type electrodes, and highly active hydrogen radicals are introduced into the substrate. Inductively coupled devices can also be used in the same way. Appropriate substrate temperature is about 150°C to 300°C. The reason for this will be explained later. The higher the hydrogen concentration introduced into the film, the lower the trap density Nt present at grain boundaries. As can be seen from equation (1), if Nt decreases, the ON current will decrease. 1 becomes larger. Figure 2 shows the trap density Nt existing at the grain boundaries of a polycrystalline silicon thin film and the ON current of a thin film transistor. .

It is a diagram showing which relationship. The figure shows the experimental results obtained by the inventor. Figure 2 shows the data of the Nch) transistor, and the vertical axis is the ON current (2) when the source-drain voltage Vdm = 5V and the gate-source voltage V, , = 16V. 0, and the horizontal axis represents the trap density Nt existing at the grain boundary. After plasma treatment, Nt=4~5×10 c
If it becomes about m-2, it will be difficult. . = 100 to 180 μA, and even if further plasma treatment is performed and hydrogen is introduced, it will not work. .

does not increase. The amount of hydrogen atoms contained in a polycrystalline silicon thin film with Nt = 4 to 5 x 10 am-2 is determined by SIMS.
As a result of analysis, approximately 0.09 atomic% hydrogen was detected. Therefore, there is no need to introduce more hydrogen than this, and the amount of hydrogen introduced into the film by plasma treatment is Q
, less than about latomic% is sufficient. Furthermore, when a large amount of hydrogen is introduced, hydrogen is injected not only into the grain boundaries but also into the crystalline regions, potentially causing defects. Furthermore, excessive hydrogen is considered to have an adverse effect on the stability or reliability of device characteristics. Therefore, it is desirable that the amount of hydrogen introduced into the film be less than about O, atomic %.

As shown in FIG. 5E, a thin film transistor is completed by forming contact electrodes 1-10 in the source and drain regions. As the contact electrode material, a metal material such as aluminum, chromium, or nickel is used.

Next, Example 2 of the present invention will be explained using F111! in FIG. The explanation will be given according to the process diagram of the transistor. Same figure (,a)
, a non-monocrystalline silicon thin film 3-2 is deposited on an insulating amorphous material 3-1 such as an insulating amorphous substrate such as glass or quartz or an insulating amorphous substrate layer such as 5i02. let The deposition method has been described previously and is omitted here. 3-3 shows the grain boundary, a s - d
e p o, the crystal grain size of the antinode is small and there are many defects.

Note that, although FIG. 3A shows a case in which a polycrystalline silicon thin film is deposited, an amorphous silicon thin film or a microcrystalline silicon thin film may be deposited.

Next, as shown in FIG. 4B, the silicon thin film 3-2 is crystal-grown to grow a polycrystalline silicon thin film 113-4. If the silicon ffj13-2 is amorphous or microcrystalline, solid phase growth is effective. The substrate is placed in an inert gas atmosphere such as nitrogen gas, and heated to 500°C to 700°C.
When crystallization is annealed for several to hundreds of hours at a low temperature of .degree. C., in-phase growth occurs and the crystal grain size grows to a size of several thousand micrometers. Further, if the silicon thin layer [13-2] is polycrystalline, silicon ions are implanted into the polycrystalline to make the polycrystalline amorphous, and then the solid phase growth method described above is performed to grow the crystal. Because the crystal grain size becomes larger, the third
As shown in Figure (b), the interval between grain boundaries 3-3 becomes larger. Other crystal growth methods include laser annealing recrystallization, electron beam annealing recrystallization, and melting recrystallization using a carbon strip heater. The solid-phase growth method is an extremely effective method that can be applied to low-temperature processes of about 700° C. or lower.

Next, as shown in FIG. 2C, a gate oxide film 3-5 is formed. In the plasma CVD method, the gate oxide film is deposited at about 200.degree. C., and in the CVD method, the gate oxide film is deposited at about 400.degree. Further, the sputtering method can form the film at a low temperature of about room temperature to 300°C. Other methods such as plasma oxidation, high-pressure oxidation, and laser oxidation allow gate oxide films to be formed at low temperatures. It goes without saying that a normal thermal oxidation method may be used. Regarding the thermal oxidation method, see Example 1
Since it was mentioned in the section above, it will be omitted here.

Subsequently, as shown in FIG. 3D, a gate electrode 3-6 is formed, and then an impurity element is ion-implanted using the gate electrode 3-6 as a mask to form a source region 3-7 and a drain region 3-7. form 8. Phosphorus, arsenic, boron, etc. are used as the impurity elements. Subsequently, the glabella insulating film 3-9 is formed by LPCVD method, APCVD method, sputtering method,
Deposition is performed by a method such as an ECR plasma CVD method or a photo CVD method. Thereafter, for the purpose of activating the source region and drain region and densifying the interlayer insulating film,
Heat treatment is performed at approximately 000°C. Next, plasma treatment is performed. 3-10 indicates a highly active hydrogen radical. Since the plasma treatment was described in the section of Example 1, it will be omitted here.

As shown in FIG. 3E, a thin film transistor is completed by forming contact electrodes 3-11 with the source and drain regions.

Note that FIGS. 1 and 3 are an example of the manufacturing process, and the process of exposing the semiconductor element to the plasma atmosphere
．． It can be performed before the formation of electrodes 3-6 or after the formation of electrodes 10 and 3-11.

Also, by doping impurities into the channel region, Vt
It is also possible to control the hl threshold voltage). When plasma treatment is performed with hydrogen or ammonia, etc., the N-channel transistor shifts vth in the depletion direction, and the P-channel transistor shifts in the enhancement direction.
Vth can be controlled by doping with an impurity of about 10 m''.For example, in Fig. 1, before forming the gate electrode, impurities such as B (boron) are added to the There are methods such as implanting with a dose of about 1013/cm2.In particular, if the dose is about the above value, vth should be controlled so that the off-state current of both the P-channel transistor and the N-channel transistor is minimized. Therefore, even when forming a CMOS type TPT element, P c h, N c
It is also possible to do channel doping over the entire surface in the same process without selectively doping h.

As mentioned above, in conventional hydrogen plasma processing, defects frequently occur due to plasma damage, making it difficult to put it into practical use. The cause is not clear at present, but due to being immersed in the plasma atmosphere, charge-up occurs and voltage is applied to the gate film, and the substrate temperature is about 3°C. It's a kind of BT because it has a high target.
(Bias-Temperature) TP due to stress
Our model, which assumes that a defective T has occurred, explains the phenomenon well.

Therefore, in order to reduce defects due to plasma damage, (
1) Prevent charge-up. (2) Lower the substrate temperature during plasma processing. It is predicted that the countermeasures will be effective. In fact, our research has revealed that by taking such measures, damage caused by plasma damage can be significantly reduced. The details are described below.

First, a method for preventing charge-up will be described.

To prevent charge-up, (1) Process in asymmetric plasma. (2) Reduce radio frequency (RF) power using ammonia gas. (3) Plasma treatment is performed with a conductive thin film formed on the surface. Our study revealed that the following measures are effective.

(1) Processing in an asymmetric plasma.

We investigated the correlation between plasma conditions and damage in order to completely eliminate damage caused by plasma damage. The results revealed the following.

(a) When plasma processing is performed in a parallel plate plasma CVD apparatus, damage due to plasma damage is less likely to occur if the plasma is asymmetric between the electrode side that applies high frequency and the electrode side that holds the substrate. Particularly, no damage occurred in asymmetric plasma where a strong plasma light emitting region occurs only on the substrate side to which high frequency waves are applied, and no strong plasma light emitting region exists on the substrate side. That is, in a single-wafer type plasma CVD apparatus that processes substrates of about 6 inches to 8 inches or less one by one, the plasma tends to become asymmetrical, so it has become clear that this apparatus is most suitable as a hydrogen plasma processing apparatus.

(b) The larger the parallel plate plasma CVD equipment becomes, the more
The symmetry of the plasma improves, making it easier to cause damage. As a result, mass production of plasma treatment processes has become extremely difficult. However, even in a large plasma CVD apparatus, if the area ratio of the electrodes on the high frequency application side and the substrate side is changed, the symmetry of the plasma can be disrupted. It is important to make the electrode area on the high frequency application side smaller than that on the substrate side. In particular, the high frequency side should be approximately 0.8 times or less than the board side (
If the area is desirably about 0.5 times or less), the symmetry of the plasma will be disrupted, making it difficult to cause damage.

(C) Increasing the electrode spacing can also break the symmetry of the plasma and suppress damage. Specifically 40
If the electrode spacing is set apart by at least 60 mm, preferably at least 60 mm, damage will be significantly reduced.

As described above, by processing in an asymmetric plasma, defects due to plasma damage can be completely eliminated and TPT characteristics can be significantly improved.

(2) Reduce radio frequency (RF) power using ammonia gas.

In the hydrogen plasma treatment method, a halogen gas such as hydrogen gas or chlorine gas is introduced into a reaction chamber of a plasma CVD apparatus or the like, and the substrate is further heated to about 150°C to 300°C.

Next, high frequency energy of, for example, 0.2 to 0°7 W/Cm" (depending on the device) is applied,
This is carried out by a method such as bringing the gas into a chemically active state and immersing the semiconductor device in the plasma atmosphere for about 30 minutes to 2 hours.

Furthermore, 0. 2-0. If the power is lowered below about 7 W/cm, the effect of improving characteristics will be drastically reduced.

On the other hand, in the plasma processing method using ammonia gas according to the present invention, ammonia gas is introduced into a reaction chamber of a plasma CVD apparatus or the like, and the substrate is further heated to about 150°C to 300°C. Then, for example, 0. 05~0. I
applying high frequency energy of the order of W/am'' (depending on the device) to bring the gas into a chemically active state;
This is done by immersing the semiconductor device in the plasma atmosphere for about 30 minutes to 2 hours. Compared to hydrogen plasma treatment, the same or higher TPT can be achieved with less than a quarter of the power.
This had the effect of improving the characteristics, and the field effect mobility of the Nch TFT became approximately 50 to 60 am2/V-8eC.

Furthermore, there were no defects due to plasma damage. The reason why ammonia gas is effective even at lower power is not clear at present, but ammonia gas is more likely to become chemically active than hydrogen gas at low power; The hypothesis is that a high power must be applied. It has been confirmed that even with the same power, ammonia gas causes fewer defects due to plasma damage.

(3) Plasma treatment is performed with conductive y*m formed on the surface.

In the embodiment shown in FIG. 1, in step (b), 1l of glabellar insulation
After forming 1-8, hydrogen plasma treatment is performed in step (C). However, a conductive thin film is formed on the glabella insulation 1 [1-8, and the conductive thin film and the substrate holder are electrically connected. As a result of our studies, it has become clear that preventing charge-up by connecting the battery and applying plasma treatment is also effective in significantly reducing damage. When forming a conductive thin film on the entire surface, (a) a metal such as Al or Cr is formed by sputtering or the like to a thickness of less than 500, preferably less than 300. (b) Polycrystalline silicon doped with impurities is formed by CVD or the like. The following methods are effective. In the case of (a), if the metal film thickness is increased to 500 A or more, it becomes difficult for hydrogen active species to pass through the metal, and the effect of improving characteristics is significantly reduced. In the case of (b), since active hydrogen species easily pass through polycrystalline silicon, sufficient improvement in characteristics can be seen even if the film thickness is increased, for example, by about 5,000 or less. Is the conductive thin film dense like this?
By optimizing the film thickness depending on whether it is porous or not,
It is possible to significantly reduce damage caused by charge-up while maintaining sufficient characteristics improvement.

Next, a method of lowering the substrate temperature during plasma processing will be described. The optimum value for the substrate temperature is between about 150°C and 300°C, but when it approaches 300°C, the above-mentioned BT
Defects such as TPT gate withstand voltage failure and vth shift due to stress become noticeable.

Therefore, when the substrate temperature is lowered to less than 250°C, the effect of reducing damage begins to appear, and when it is lowered to less than 200°C, almost no defects are observed. However, it has become clear that lowering the substrate temperature not only reduces damage but also reduces the effect of improving device characteristics. In that case, after the plasma treatment, the semiconductor device is heat-treated in an atmosphere containing at least hydrogen, so that the substrate temperature can be lowered to 20.
Even when plasma processing is performed at a temperature below 0°C, the substrate temperature is 300°C.
Device characteristics almost equivalent to those obtained by plasma treatment at ℃ were obtained with almost no damage.

The heat treatment is effective at a temperature of 300°C or higher; however,
In order to obtain a sufficient effect, it is necessary to perform heat treatment at a high temperature of about 350°C to 450°C for about 30 minutes to 2 hours. Further, as the gas introduced during the heat treatment, there is a method in which hydrogen is diluted with nitrogen, argon, etc., but it was particularly effective to use only hydrogen and conduct the heat treatment in a hydrogen atmosphere. or,
Heat treatment after plasma treatment not only improves characteristics but also improves vth
It also has the effect of recovering damage from Shift, etc.

In addition to the measures described above, damage can be reduced by devising the pattern shape of the semiconductor element. That is, taking TPT as an example, non-single crystal silicon gi antinode 1-
If either the pattern of the gate electrode 2 or the gate electrode 1-5 is sufficiently long compared to the other, damage to a particular TFi tends to occur easily. Taking the case of a liquid crystal display device as an example, the TPT provided in each pixel is made of silicon thin 1 liter.
-2 is independent for each TFT, whereas gate electrodes 1-5 are common to all TFTs in one column. If there is in-plane variation in the amount of charge-up due to exposure to plasma, the gate electrode will have almost the same potential, but the silicon thin film of each pixel will have a different potential depending on the amount of charge-up. There are likely to be TFTs in which the difference in potential between the gate electrode and the silicon thin film becomes large. the result,
It has been found that damage is more likely to occur with certain TPTs. In that case, if plasma treatment is performed with the gate electrodes separated for each pixel or for each pixel, and these separated gate electrodes are electrically connected in a subsequent process, the above-mentioned damage will not occur at all. In addition, on the contrary, silicon thin film-2 is formed into a long and narrow island shape, and TPT is formed on the island.
When a plurality of gate electrodes 1-5 are formed and the gate electrodes 1-5 are separated, the same effect can be obtained by separating the island-shaped silicon thin film into islands for each TFT or a plurality of TFTs.

As described above, by applying the present invention, it is possible to manufacture highly reliable thin film transistors with large ON current, small OFF current, steep rise in the subthreshold region, and no defects due to plasma damage. becomes. Note that the effects of the damage reduction measures described above can be further enhanced by implementing a plurality of measures at the same time.

For example, a method of lowering the substrate temperature to less than about 200° C. and processing in an asymmetric plasma is also extremely effective.

As an application of the present invention, for example, when the present invention is applied to an active matrix substrate, a high-definition panel with a built-in driver can be realized. In addition, if it is used in an image sensor that integrates a shift register circuit and a photoelectric conversion element on the same substrate, it can be used for high-speed reading, large size such as A3 size, or
Great effects can be expected for colorization, etc. Since the driving voltage can also be reduced, it is useful for reducing power consumption and further improving reliability. Further, as explained in Example 2, by applying the present invention to a low temperature process of about 700° C. or less, a large-area, high-performance semiconductor device can be realized.

FIG. 4 shows a cross-sectional view of an image sensor in which a shift register circuit and a photoelectric conversion element are integrated on the same substrate as an example of the application of the present invention. In Figure 4, 4-1 is glass;
Amorphous insulating substrate such as quartz, 4-2 a gate insulating layer, 4-
3 is a gate electrode, 4-4 is a source/drain region, 4-
5 is an insulating film between the eyebrows, 4-6 is a lower transparent electrode of the photoelectric conversion element, 4-7 is an amorphous silicon layer, and 4-9 is an upper electrode and wiring of the photoelectric conversion element. In addition, in Figure 4, for simplicity,
Only a cross-sectional view of a TPT forming a photoelectric conversion element and its pixel SW is shown. The details of the method for forming TPT have been described with reference to FIGS. 1 and 3, and will therefore be omitted here. After exposing the semiconductor element to a plasma atmosphere containing at least one of hydrogen and ammonia, glabellar insulation II! A transparent electrode serving as the lower electrode of the photoelectric conversion element is formed on 4-5. The transparent electrode is formed by forming and patterning ITOlSnOa or the like by sputtering or the like. Next, plasma C
An amorphous silicon layer forming a photoelectric conversion layer is formed using a VD method or the like, and after patterning, a contact hole is made in the glabella insulation B4-5, and a metal material such as A1, C, or r is used to form a contact hole on the wiring and the upper part of the photoelectric conversion element. Electrodes are formed in the same process. By performing the plasma treatment of the present invention, the TPT characteristics were improved as described above, and the scanning speed of the shift register was improved. Conventional image sensor is A4 200DP with 5ms/li
What used to be A4 200D according to the present invention
With PI, we were able to increase the speed to 1mS/line. This has a great effect on increasing the length of image sensors and realizing color image sensors.

Although FIGS. 1 to 4 show an example in which the present invention is applied to a poly-SiTFT manufacturing process, the present invention is not limited thereto. The present invention is effective for all insulated gate field effect transistors in which at least a portion of the channel region is polycrystalline. The present invention is also effective in transistors in which at least a portion of the channel region is made of microcrystals, and in transistors in which a portion of the channel region is made of an insufficiently hydrogenated amorphous semiconductor formed by sputtering, vapor deposition, etc. It is.

Moreover, even if the channel region is single crystal, three-dimensional IC
When an element is formed in a silicon layer that has been recrystallized or grown in a solid phase, defects such as sub-grain boundaries are likely to occur in the crystal.

In this case, the characteristics can be effectively improved by terminating the defects using the semiconductor device manufacturing method according to the present invention.

Furthermore, the present invention is also effective for reducing the defect density at the heterojunction interface of HBTs (hetero-bipolar transistors) and the like. In particular, when at least one of the two semiconductor layers forming the heterojunction is made of a non-single crystal semiconductor, the plasma treatment according to the present invention can simultaneously reduce defects in the film and at the interface.

Furthermore, the present invention can be widely applied to semiconductor processes in general, including solar cells, optical sensors, bipolar transistors, and static induction transistors using non-single crystal semiconductors as element materials.

[Effects of the Invention] As described above, according to the present invention, poly-5iTF
It is possible to improve the performance of an insulated gate field effect transistor in which at least a portion of the channel region, such as T, is made of a non-single crystal semiconductor without causing defects due to plasma damage or the like. Further, the present invention can be widely applied not only to insulated gate field effect transistors but also to semiconductor processes in general, and its effects are extremely large.

[Brief explanation of drawings]

- Figures 1(a) to 1(e) are process diagrams of the thin film transistor according to the present invention. Figure 2 shows T existing at the grain boundaries of a polycrystalline silicon thin film.
rap density Nt and f311! Transistor ON current engineer. . It is a diagram showing which relationship. Circles indicate experimental values, and solid lines indicate calculated values. FIGS. 3(a) to 3(e) are process diagrams of the thin film transistor according to the present invention. FIG. 4 is a sectional view of the image sensor according to the present invention. 1-1. 3-1. 4-1; Insulating amorphous material 1-
2. 3-2; Non-single crystal thin film - 9°: Hydrogen radical; Above grain boundary Applicant Seiko Epson Co., Ltd. Attorney Kizo Tsuchi Suzuki (and 1 other person) Figure 2 Figure 3

Claims (10)

[Claims] (1) A semiconductor device in which at least a portion of a channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, characterized in that the semiconductor device is immersed in a plasma atmosphere containing at least ammonia. (2) In a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, immersing the semiconductor device in an asymmetric plasma atmosphere containing at least one of hydrogen and ammonia is recommended. Characteristic semiconductor devices. (3) In a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the semiconductor device is immersed in a plasma atmosphere containing at least one of hydrogen and ammonia. A semiconductor device characterized by being heat-treated in an atmosphere containing hydrogen. (4) The substrate temperature when immersed in the plasma atmosphere is 20°C.
4. The semiconductor device according to claim 3, wherein the temperature is less than 0°C. (5) The semiconductor device according to claim 3, wherein the heat treatment temperature is 300°C to 450°C. (6) A method for manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, including at least the step of immersing the semiconductor device in a plasma atmosphere containing at least ammonia. A method for manufacturing a semiconductor device. (7) In a method of manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the step of immersing the semiconductor device in a plasma atmosphere containing at least one of hydrogen and ammonia. 1. A method for manufacturing a semiconductor device, characterized in that the plasma is asymmetric. (8) A method for manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, a step of immersing the semiconductor device in a plasma atmosphere containing at least one of hydrogen or ammonia; 1. A method for manufacturing a semiconductor device, comprising at least the step of heat-treating the semiconductor device in an atmosphere containing at least hydrogen. (9) The substrate temperature in the step of immersing in the plasma atmosphere is 2.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the temperature is less than 00°C. (10) The heat treatment temperature in the heat treatment step is 300°C to 4°C.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the temperature is 50°C.