JPH02278753A - Thin package equipment - Google Patents
Thin package equipmentInfo
- Publication number
- JPH02278753A JPH02278753A JP1099327A JP9932789A JPH02278753A JP H02278753 A JPH02278753 A JP H02278753A JP 1099327 A JP1099327 A JP 1099327A JP 9932789 A JP9932789 A JP 9932789A JP H02278753 A JPH02278753 A JP H02278753A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- substrate
- lead
- resin
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 16
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 235000010678 Paulownia tomentosa Nutrition 0.000 description 1
- 240000002834 Paulownia tomentosa Species 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 239000005355 lead glass Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はIc等の薄型パッケージ装置に係り、特に特性
を損なうことなく小型、3型化を実現して適用分野の拡
大を図った薄型パッケージ装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a thin package device such as an IC, and in particular, a thin package that has been made smaller and three-inch without impairing its characteristics, thereby expanding the field of application. Regarding equipment.
3、発明の詳細な説明
〔4既 要〕
IC等半導体装置で特に薄型パッケージ装置に[従来の
技術]
近年、LSIの高集積化につれて多ピン化1表面実装化
の傾向が益々強まっているが、最近では特に薄型化を図
るためにフラットパッケージICが使用されるようにな
っている。3. Detailed description of the invention [4 Already required] Semiconductor devices such as ICs, especially thin package devices [Prior art] In recent years, as LSIs have become highly integrated, there has been a growing trend towards multi-pin single surface mounting. Recently, flat package ICs have come into use especially in order to reduce the thickness of the ICs.
第3図は従来のフラットパッケージICの構成を示す断
面図である。FIG. 3 is a sectional view showing the structure of a conventional flat package IC.
図で、11はICチップ(以下素子とする)、12はリ
ードフレームの素子搭載用ステージであり、13は上記
素子11上の複数の電極とそれぞれ対応するように該ス
テージ12の周囲に放射状に形成されている複数のリー
ドを示し、 14は上記素子11上の各ハンプ電極と該
各ハンプ電掻に対応する上記リード14の間を接続して
いるワイヤ、15は該素子11をステージ12.リード
13およびワイヤ14と共に封入して一体化させている
エポキシ樹脂を示している。In the figure, 11 is an IC chip (hereinafter referred to as an element), 12 is a stage for mounting an element on a lead frame, and 13 is a stage radially arranged around the stage 12 so as to correspond to a plurality of electrodes on the element 11. A plurality of leads formed are shown, 14 is a wire connecting each hump electrode on the element 11 and the lead 14 corresponding to each hump electrode, 15 is a wire connecting the element 11 to a stage 12. The epoxy resin is shown encapsulated and integrated with the leads 13 and wires 14.
構成の工程を簡単に説明すると、リードフレームの素子
搭載用ステージ12の所定位置に素子11を搭載してダ
イスボンディングによって該素子11をステージ■2に
固定した後、該素子11上の複数の各バンプ電極と該ス
テージの周囲に形成されている各対応リード13の間を
ワイヤボンディングマシーンによってワイヤ14で自動
的に接続する。To briefly explain the construction process, after mounting the element 11 at a predetermined position on the element mounting stage 12 of the lead frame and fixing the element 11 to the stage 2 by die bonding, each of the plurality of elements on the element 11 is A wire 14 is automatically connected between the bump electrode and each corresponding lead 13 formed around the stage using a wire bonding machine.
その後、該素子11を含むリード13の所定位置までの
領域を上記ステージごと埋没させるようにエポキシ樹脂
で封入してフラットパッケージICを構成している。Thereafter, the area including the element 11 up to a predetermined position of the lead 13 is sealed with epoxy resin so as to bury the stage together, thereby forming a flat package IC.
かかる構成になるパッケージICでは、■ステージ12
の裏面からステージ12の樹脂との接触面を伝わって水
分が素子11に浸入し易いため、ステージ12の裏面ま
で耐湿不良が生じない厚さの樹脂で被覆する必要がある
。In a package IC with such a configuration, ■ Stage 12
Since moisture easily enters the element 11 from the back surface of the stage 12 through the contact surface with the resin of the stage 12, it is necessary to cover the back surface of the stage 12 with a resin having a thickness that does not cause poor moisture resistance.
■ワイヤボンディングマシーンによる接続の場合にはワ
イヤ14に余長を持たせて接続するため、素子11の表
面より更に図示3寸法だけパッケージICとしての厚さ
を厚くする必要がある。(2) In the case of connection using a wire bonding machine, since the wire 14 is connected with extra length, it is necessary to make the package IC thicker than the surface of the element 11 by three dimensions shown in the figure.
等の理由によってパッケージICとしての厚さを薄くす
ることに制約が生じ、最低でも1mm程度になることか
ら特に薄いICを必要とする分野には適用できない欠点
がある。For these reasons, there are restrictions on reducing the thickness of a packaged IC, which is at least about 1 mm, which has the disadvantage that it cannot be applied to fields that require particularly thin ICs.
従来のフラットパッケージタイプのICではその薄型化
に制約があるため適応分野に制限が生じ、特に薄型を必
要とする高密度実装用プリント板やICカード等には使
用できないと言う問題があった。Conventional flat package type ICs have restrictions on their thinness, which limits their applicability, and there is a problem in that they cannot be used for high-density mounting printed boards, IC cards, etc., which require a particularly thin thickness.
(課題を解決するための手段〕
上記問題点は、基板表面の中央に形成された凹部に素子
が搭載され、
該凹部の周囲の基板上に外部導出用リードが配置さ4、
咳素子と外部導出用リードが接続用リードにより接続さ
れ、
該基板表面側の素子、接続用リードおよび外部導出用リ
ードが樹脂で覆われ且つ該凹部の形成さ机た部分の基板
裏面が樹脂で覆われずに封止されてなる薄型パッケージ
装置によって解決される。(Means for Solving the Problems) The above problem is that the device is mounted in a recess formed in the center of the substrate surface, and the external leads are arranged on the substrate around the recess. The lead-out lead is connected by the connection lead, the element on the front side of the board, the connection lead, and the external lead-out lead are covered with resin, and the back side of the board where the recess is formed is not covered with resin. The problem is solved by a thin package device that is sealed.
されている素子搭載用ステージ裏面側の絶縁樹脂層が除
去できれば該樹脂1分の厚さを削減することができる。If the insulating resin layer on the back side of the element mounting stage can be removed, the thickness of the resin can be reduced by one minute.
また素子のバンプ電極と周囲リード線との接続を従来の
ワイヤボンディングのワイヤからテープリードボンディ
ングによる接続用リード変えると、余長すなわち撓みが
必要なくなって表面側の樹脂の厚さが削減できる。Furthermore, if the connection between the bump electrode of the element and the peripheral lead wire is changed from the conventional wire bonding wire to the connection lead by tape lead bonding, the extra length, that is, the bending, is no longer necessary, and the thickness of the resin on the surface side can be reduced.
本発明では、素子搭載部分に凹みが形成され。In the present invention, a recess is formed in the element mounting portion.
その凹みの周囲にリードが配置される基板をベースとし
て使用することによってステージ裏面側の絶縁樹脂層の
除去を可能とし、更にテープ・オートメイテッド・ポン
デイ゛ング手段等によるリード接続を併用することによ
ってICとして耐湿特性を良好に薄型化の実現を図って
いる。By using the substrate on which the leads are arranged around the recess as a base, it is possible to remove the insulating resin layer on the back side of the stage, and furthermore, by using a combination of lead connection using tape automated bonding means, etc. The aim is to achieve a thinner IC with good moisture resistance.
従って、特性を落とすことなくICとしての小型、″a
型化を実現することができる。Therefore, it can be made compact as an IC without degrading its characteristics.
It is possible to realize moldization.
1作 用〕
従来のフラットパッケージタイプのICに使用〔実施例
〕
第1図は本発明になる薄型パッケージ装置の製遣方法を
示す工程図であり、第2図は他の実施例を示す図である
。1. Function] Used in conventional flat package type IC [Example] Fig. 1 is a process diagram showing a manufacturing method of a thin package device according to the present invention, and Fig. 2 is a diagram showing another embodiment. It is.
以下図に従って説明する。The explanation will be given below according to the figures.
第1図(八)で、1は秩(Fe) 、 桐(Cu) 、
アルミニウム(八りまたはこれらの合金等からなる例え
ば厚さが100μm程度の基板であり、その中央部の少
なくとも素子面積より多少大きいステージ18部分は板
厚とほぼ等しい段差d (100μm)の開平面に形成
されている。なお素子を搭載しまた外部導出用のり一ト
を配置する基板をこのように金属材f」によって形成す
れば、薄く且つ高い強度に形成できると共に素子からの
熱の放散もよい。In Figure 1 (8), 1 is Chichi (Fe), Kiri (Cu),
The substrate is made of aluminum or an alloy thereof, and has a thickness of, for example, about 100 μm, and the central portion of the stage 18, which is at least slightly larger than the element area, is an open plane with a step d (100 μm) that is approximately equal to the thickness of the plate. If the substrate on which the element is mounted and the adhesive for leading to the outside is arranged is formed of the metal material f'' in this way, it can be formed thin and with high strength, and the heat from the element can be dissipated well. .
そこで該基板lの上記ステージ1aの中央部の搭載素子
とほぼ同じ面積頭載に厚さ10μm程度の半田や接着剤
の如き接合固定11U l bを被着形成すると共に該
領域を除く該基板1の表裏はぼ全面に同じ旋さの例えば
ホーローの如き絶縁膜1cをコーティング処理して形成
した後、上記ステージ1aの全周辺に沿う凸面上の該絶
縁膜1この所定幅領域に厚さ10μm程度の例えば鉛ガ
ラスの如き低融点ガラスやポリイミドの様な耐熱性樹脂
からなる絶縁層接着剤層1dを上記同様のコーティング
処理で被着形成する。Therefore, a bonding fixing material 11Ulb such as solder or adhesive with a thickness of about 10 μm is formed on the substrate 1 in an area approximately the same as the mounting element in the center of the stage 1a, and the substrate 1 is removed from the area. After coating almost the entire surface of the front and back surfaces of the insulating film 1c, such as enamel, having the same helix, the insulating film 1 is placed on the convex surface along the entire periphery of the stage 1a to a thickness of about 10 μm in this predetermined width region. An insulating adhesive layer 1d made of a low melting point glass such as lead glass or a heat resistant resin such as polyimide is formed by coating in the same manner as described above.
図(B)はこの状態を示している。Figure (B) shows this state.
一方図(C)の外リード2は、鉄(Fe) 、 ’A
(Cu) 。On the other hand, the outer lead 2 in figure (C) is made of iron (Fe), 'A
(Cu).
アルミニウム(A ffi )またはこれらの合金等か
らなる厚さ50μmの金属板をエツチング等の手段で形
成したもので、所定の被搭載素子上の複数のバンプ電極
に対応して幅40μm程度の複数の外部導出用リード2
a、2b、2c、2d −を周辺連結部(2z)から中
心に向かう逆放射の櫛刃状になっており、核外リード2
の外部導出用リード2a、 2b、 2c、 2d・・
・の各先端部が上記図(11)の絶縁層1d上の所定位
置になるように例えばポリイミドのような耐熱性接着材
で接着固定して図(C)に示すリードベース3を形成し
ている。A metal plate with a thickness of 50 μm made of aluminum (Affi) or an alloy thereof is formed by means such as etching, and a plurality of bump electrodes with a width of about 40 μm are formed in correspondence with a plurality of bump electrodes on a predetermined mounted element. External lead lead 2
The extranuclear lead 2
External leads 2a, 2b, 2c, 2d...
The lead base 3 shown in Figure (C) is formed by adhering and fixing each tip of . There is.
他方平面図(D)に示す5は、例えば上記基板1とほぼ
同じ大きさの角孔6aを備えたポリイミド等からなる樹
脂フィルム6の片面に、上記角孔6aから該角孔6aの
内側に向かって突出する内側端部[!1が所定の素子上
の複数の電極位置に対応しまた該角孔6aの端部E2が
図(C)に示すリードベース3の各外部導出用リード2
a、 2b、 2c、 2d・・・の先端部に対応する
ようにパターニング形成した銅(Cu)またはその合金
からなる複数の接続用リード5a、5b、5c。On the other hand, 5 shown in the plan view (D) is formed on one side of a resin film 6 made of polyimide or the like having a square hole 6a of approximately the same size as the substrate 1, from the square hole 6a to the inside of the square hole 6a. The inner end that protrudes toward [! 1 corresponds to a plurality of electrode positions on a predetermined element, and the end E2 of the square hole 6a corresponds to each external lead 2 of the lead base 3 shown in FIG.
A, 2b, 2c, 2d, etc. A plurality of connection leads 5a, 5b, 5c made of copper (Cu) or an alloy thereof are patterned to correspond to the tips of the leads 5a, 2b, 2c, 2d, .
5d・・・を持つ回路基板を示したものである。5d... shows a circuit board with...
そこで、破線L1で示す所定領域に素子7を載置した上
で該素子7上の各ハンプ電極と上記回路基板5の各接続
用リードの内側端部E1を半田付は等の手段でボンディ
ング接続すると図(E)に示すチップ完成体8を得るこ
とができる。Therefore, after placing the element 7 in a predetermined area indicated by the broken line L1, each hump electrode on the element 7 and the inner end E1 of each connection lead of the circuit board 5 are bonded by soldering or other means. Then, a finished chip 8 shown in FIG. 8(E) can be obtained.
かかる回路基板5を使用したチップ完成体8の場合には
、テープ状の各接続用リード5a、5b、5c、5d・
・・は平面的に形成されるためワイヤボンディング手段
におけるワイヤのようにボンディング時に余長を持たせ
る必要がなく、結果的に薄型化に対して効果的な接続を
実現することができる。In the case of a completed chip 8 using such a circuit board 5, tape-shaped connection leads 5a, 5b, 5c, 5d,
Since the wires are formed planarly, there is no need to provide extra length during bonding unlike the wires used in wire bonding means, and as a result, an effective connection can be realized for thinning.
次いで、該チップ完成体8の素子7の裏面側を前記リー
ドベース3の接合固定膜1b面とに載置してダイス付け
を行うと共に、該チップ完成体8の各接続用リード5a
、 5b、 5c、 5d・・・の図(D)および図(
E)におけるE2部分をそれぞれ対応する外リード2の
各外部導出用リード2a、 2b、 2c、 2d・・
・の内側端部にボンディング接続すると共に図(D)お
よび図(E)の−点鎖線L2で示す線上で各接続用リー
ドを切断すると図(F)に示す如き状態とすることがで
きる。Next, the back side of the element 7 of the completed chip body 8 is placed on the surface of the bonding fixing film 1b of the lead base 3 to perform dicing, and each connection lead 5a of the completed chip body 8 is
, 5b, 5c, 5d... Figure (D) and Figure (
The E2 portion in E) is connected to each external lead-out lead 2a, 2b, 2c, 2d, etc. of the corresponding outer lead 2.
When bonding is made to the inner end of . . , and each connection lead is cut along the line shown by the dashed-dotted line L2 in FIGS. (D) and (E), a state as shown in FIG. (F) can be obtained.
ここで、基板1の裏面側を露出させた状態で少なくとも
上記チップ完成体8が埋没するように図の一点鎖線L3
で示す領域を通常の低圧トランスファーモールディング
方法によってエポキシ樹脂等で封入してパッケージ化す
ると共に、図(C)の二点鎖線L4で示すc ”−c、
、線で外リード2の周辺連結部2zを切断除去するこ
とによって図(G)に示すような所要の薄型パッケージ
装置9を構成することができる。Here, in a state where the back surface side of the substrate 1 is exposed, at least the above-mentioned completed chip body 8 is buried under the dotted chain line L3 in the figure.
The area indicated by is sealed with epoxy resin or the like by a normal low-pressure transfer molding method and packaged, and the area indicated by the two-dot chain line L4 in Figure (C) is c''-c,
By cutting and removing the peripheral connecting portion 2z of the outer lead 2 with the lines , it is possible to construct the required thin package device 9 as shown in Figure (G).
なお、従来と同様の素子を使用した場合に、パッケージ
装置としての全体の厚さが約0.5mm以下で構成でき
ることを実験的に確認している。In addition, it has been experimentally confirmed that when using elements similar to the conventional one, the overall thickness of the package device can be configured to be approximately 0.5 mm or less.
第2図は特に素子の発熱量が多い場合に適用される例を
示したものである。FIG. 2 shows an example in which the method is applied particularly when the amount of heat generated by the element is large.
この場合には第1図(B)の工程で基板1の紙面下側す
なわち裏面の所定領域にエポキシ樹脂の如き絶縁性接着
剤膜1eを介して半田IJi 1 fを形成すると共に
他の部分を第1図で説明した如くに形成して図(a)に
示す状態とする。In this case, in the process shown in FIG. 1(B), solder IJi 1f is formed on a predetermined area of the lower side of the paper surface of the substrate 1, that is, the back surface, through an insulating adhesive film 1e such as epoxy resin, and other parts are It is formed as explained in FIG. 1 to obtain the state shown in FIG. 1(a).
次いで、第1図で説明した工程を経て所要の薄型パッケ
ージ装置を構成した後、上記半田1191 fの面に通
常の放熱フィンIQを添着して図(b)に示すような放
熱フィンが装着された薄型パッケージ装置を得ることが
できる。Next, after configuring the required thin package device through the steps explained in FIG. 1, a normal heat dissipation fin IQ is attached to the surface of the solder 1191f, and a heat dissipation fin as shown in FIG. 1B is attached. A thin package device can be obtained.
上述の如く本発明により、ICとしての特性を(員なう
ことなく小型、薄型化を実現して適用分野の拡大を図っ
た薄型パッケージ装置を提供することができる。As described above, according to the present invention, it is possible to provide a thin package device that is small and thin without sacrificing the characteristics of an IC and expands the field of application.
遣方法を示す工程図、
第2図は他の実施例を示す図、
第3図は従来のフラットパッケージICの構成を示す断
面図である。FIG. 2 is a diagram showing another embodiment, and FIG. 3 is a sectional view showing the configuration of a conventional flat package IC.
である。図において、
1は基板、 1aは凹部(ステージ)、1bは
接合固定膜、 1cは絶縁嗅、1dは接着剤層、
1eは絶縁性接着剤膜、ifは半田膜、 2
は外リード、2a、2b・・・は外部導出用リード、2
zは連結部、3はリードベース、 5は回路基板、5
a、5b・・・は接続用リード、6は樹脂フィルム、7
は【Cチップ(素子)、8はチップ完成体、9は薄型パ
ッケージ装置、10は放熱フィン、をそれぞれ表わす。It is. In the figure, 1 is a substrate, 1a is a recess (stage), 1b is a bonding fixing film, 1c is an insulating layer, 1d is an adhesive layer,
1e is an insulating adhesive film, if is a solder film, 2
2a, 2b... are external leads, 2
z is the connection part, 3 is the lead base, 5 is the circuit board, 5
a, 5b... are connection leads, 6 is a resin film, 7
[C] represents a chip (element), 8 represents a completed chip, 9 represents a thin package device, and 10 represents a heat dissipation fin.
第1図は本発明になる薄型パッケージ装置の製第1 図
(Yの2ン
(1,、)
イt=の穴ンlセy子り11z(づ〒ぐ1フ一図第2
図
(G)
笑1図(での3)
第
図Figure 1 shows how the thin package device of the present invention is manufactured.
Figure (G) LOL Figure 1 (Part 3) Figure
Claims (1)
(7)が搭載され、 該凹部(1a)の周囲の基板(1)上に外部導出用リー
ド(2a、2b、2c、2d)が配置され、該素子(7
)と外部導出用リード(2a、2b、2c、2d)が接
続用リード(5a、5b)により接続され、該基板(1
)表面側の素子(7)、接続用リード(5a、5b)お
よび外部導出用リード(2a、2b、2c、2d)が樹
脂で覆われ且つ該凹部(1a)の形成された部分の基板
(1)裏面が樹脂で覆われずに封止されてなることを特
徴とする薄型パッケージ装置。[Claims] An element (7) is mounted in a recess (1a) formed in the center of the surface of the substrate (1), and external leads (2a) are mounted on the substrate (1) around the recess (1a). , 2b, 2c, 2d) are arranged, and the element (7
) and external lead-out leads (2a, 2b, 2c, 2d) are connected by connection leads (5a, 5b), and the board (1
) The surface side element (7), the connection leads (5a, 5b), and the external lead-out leads (2a, 2b, 2c, 2d) are covered with resin and the part of the substrate in which the recess (1a) is formed ( 1) A thin package device characterized in that the back surface is sealed without being covered with resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1099327A JP2600898B2 (en) | 1989-04-19 | 1989-04-19 | Thin package device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1099327A JP2600898B2 (en) | 1989-04-19 | 1989-04-19 | Thin package device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02278753A true JPH02278753A (en) | 1990-11-15 |
JP2600898B2 JP2600898B2 (en) | 1997-04-16 |
Family
ID=14244541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1099327A Expired - Lifetime JP2600898B2 (en) | 1989-04-19 | 1989-04-19 | Thin package device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2600898B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0488783A2 (en) * | 1990-11-30 | 1992-06-03 | Shinko Electric Industries Co. Ltd. | Lead frame for semiconductor device comprising a heat sink |
-
1989
- 1989-04-19 JP JP1099327A patent/JP2600898B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0488783A2 (en) * | 1990-11-30 | 1992-06-03 | Shinko Electric Industries Co. Ltd. | Lead frame for semiconductor device comprising a heat sink |
Also Published As
Publication number | Publication date |
---|---|
JP2600898B2 (en) | 1997-04-16 |
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