JPH02278742A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02278742A JPH02278742A JP1100417A JP10041789A JPH02278742A JP H02278742 A JPH02278742 A JP H02278742A JP 1100417 A JP1100417 A JP 1100417A JP 10041789 A JP10041789 A JP 10041789A JP H02278742 A JPH02278742 A JP H02278742A
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- lead
- semiconductor chip
- internal leads
- internal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 13
- 239000000919 ceramic Substances 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000009719 polyimide resin Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 239000010408 film Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にセラミックパッケージ
型の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a ceramic package type semiconductor device.
従来の半導体装置は第３図（ａ）（ｂ）に示すように、
セラミック基板１の中央部に設けた凹部の底面に素子載
置部を設け、前記凹部の上段水平面の内周縁部近傍に配
列して第１の内部リード２ａが設けられ、内部リード２
・ａの外周に第２の内部リード２ｂが設けられる。次に
、前記素子載置部に半導体チップ４を搭載し、半導体チ
ップ４の電極と第１及び第２の内部リード２ａ、２ｂと
を金属細線５で接続する。The conventional semiconductor device, as shown in FIGS. 3(a) and (b),
An element mounting portion is provided on the bottom surface of a recess provided in the center of the ceramic substrate 1, and first internal leads 2a are arranged near the inner peripheral edge of the upper horizontal surface of the recess.
- A second internal lead 2b is provided on the outer periphery of a. Next, the semiconductor chip 4 is mounted on the element mounting section, and the electrodes of the semiconductor chip 4 and the first and second internal leads 2a, 2b are connected with thin metal wires 5.
上述した従来の半導体装置は、多ビン化の要求に対処し
且つセラミック容器を構成するグリーンシートの積層ず
れを避ける場合、及び薄膜でリードパターンを形成する
場合においては、内部リードはセラミック容器の凹部上
段水平面に２列に設けられる。このとき、半導体チップ
と内部リードとを接続する２重のループを形成している
金属細線のうち、外側の金属細線が垂れを起こして内側
の内部リードと短絡を生じやすいという問題点があった
。In the conventional semiconductor device described above, in order to meet the demand for a large number of bins and to avoid stacking misalignment of green sheets constituting the ceramic container, and in cases where a lead pattern is formed with a thin film, the internal leads are placed in the recessed part of the ceramic container. They are provided in two rows on the upper horizontal surface. At this time, there was a problem in that among the thin metal wires forming a double loop connecting the semiconductor chip and the internal leads, the outer thin metal wires tend to sag and cause a short circuit with the inner internal leads. .
本発明の半導体装置は内側中央部に設けた凹部の底面に
素子載置部を設けたセラミック容器と、前記凹部の上段
水平面の内周縁部近傍に配列して設けた第１の内部リー
ドと、前記第１の内部リードの外周に配列して設けた第
２の内部リードと、前記第１の内部リードと前記第２の
内部リードの少くとも中間に設けた絶縁膜と、前記素子
載置部に搭載した半導体チップと、前記半導体チップの
電極と前記第１及び第２の内部リードとの間を接続する
金属細線とを有する。The semiconductor device of the present invention includes: a ceramic container in which an element mounting portion is provided on the bottom surface of a recess provided in an inner central portion; first internal leads arranged in the vicinity of an inner peripheral edge of an upper horizontal surface of the recess; second internal leads arranged around the outer periphery of the first internal leads; an insulating film provided at least between the first internal leads and the second internal leads; and the element mounting section. and a thin metal wire connecting between an electrode of the semiconductor chip and the first and second internal leads.
次に、本発明について図面を参照して説明する９
第１図（ａ＞、（ｂ）は本発明の第１の実施例を示すパ
ッケージの部分平面図及びＡ−Ａ”線断面図である。Next, the present invention will be explained with reference to the drawings.9 Figure 1 (a>, (b) is a partial plan view and a sectional view taken along the line A-A'' of a package showing a first embodiment of the present invention. .
第１図（ａ）、（ｂ）に示すように、セラミック容器１
の内側中央部に設けた四部底面に素子載置部を設け、前
記凹部の上段水平面の内側周縁部に第１の内部リード２
ａを設け、内部リード２ａの外周に内部リード２ａと千
鳥状に配列して第２のり−ド２ｂを設ける０次に、内部
リード２ａと内部リード２ｂとの中間にポリイミド系樹
脂等の帯状の絶縁膜３を選択的に設ける。次に前記素子
載置部に半導体チップ４を搭載して半導体チップ４の電
極と内部リード２ａ、２ｂとの間をそれぞれ金属細線５
により接続する。As shown in FIGS. 1(a) and (b), a ceramic container 1
An element mounting part is provided on the bottom surface of the four parts provided at the inner center part of the recess, and a first internal lead 2 is provided on the inner peripheral part of the upper horizontal surface of the recess.
a, and a second glued 2b is provided on the outer periphery of the inner lead 2a in a staggered arrangement with the inner lead 2a.Next, a strip of polyimide resin or the like is provided between the inner lead 2a and the inner lead 2b. An insulating film 3 is selectively provided. Next, the semiconductor chip 4 is mounted on the element mounting section, and thin metal wires 5 are connected between the electrodes of the semiconductor chip 4 and the internal leads 2a and 2b.
Connect by.
ここで、内部リード２ｂに接続された金属細線５は絶縁
膜３により保護されて垂れ下りによる内部リード２ａと
の短絡事故を防止できる効果がある。Here, the thin metal wire 5 connected to the internal lead 2b is protected by the insulating film 3, which has the effect of preventing short-circuit accidents with the internal lead 2a due to hanging.
第２図（ａ）、（ｂ）は本発明の第２の実施例を示すパ
ッケージの部分平面図及びＢ−Ｂ’線断面図である。FIGS. 2(a) and 2(b) are a partial plan view and a sectional view taken along the line BB' of a package showing a second embodiment of the present invention.
第２図（ａ）、（ｂ）に示すように、第１の実施例と同
様にセラミック容器の凹部上段水平面に設けた第１及び
第２の内部リード２ａ、 ２ｂを含む表面にポリイミド
系樹脂等の絶縁膜３を設け、これを選択的にエツチング
して内部リード２ａ。As shown in FIGS. 2(a) and 2(b), as in the first embodiment, polyimide resin is applied to the surface including the first and second internal leads 2a and 2b provided on the upper horizontal surface of the recess of the ceramic container. An insulating film 3 such as the above is provided, and this is selectively etched to form internal leads 2a.
２ｂの上の絶縁膜３を開口してパッド部を設けた以外は
第１の実施例と同じ構成を有しており、金属細線の垂れ
下りによる短絡事故を防止する効果を更に高める効果が
ある。This embodiment has the same structure as the first embodiment except that the insulating film 3 above the insulating film 2b is opened to provide a pad portion, and has the effect of further increasing the effect of preventing short circuit accidents due to hanging of thin metal wires. .
以上説明したように本発明は２列の内部リードの少なく
とも中間に絶縁膜を設けることにより金属細線の垂れ下
りによる内部リードとの短絡を回避できる効果がある。As described above, the present invention provides an insulating film at least between the two rows of internal leads, thereby making it possible to avoid short circuits with the internal leads due to hanging of thin metal wires.
１・・・セラミック容器、２ａ、２ｂ・・・内部リード
、３・・・絶縁膜、４・・・半導体チップ、５・・・金
属細線。DESCRIPTION OF SYMBOLS 1...Ceramic container, 2a, 2b...Inner lead, 3...Insulating film, 4...Semiconductor chip, 5...Metal thin wire.
Claims (1)
ラミック容器と、前記凹部の上段水平面の内周縁部近傍
に配列して設けた第１の内部リードと、前記第１の内部
リードの外周に配列して設けた第２の内部リードと、前
記第１の内部リードと前記第２の内部リードの少くとも
中間に設けた絶縁膜と、前記素子載置部に搭載した半導
体チップと、前記半導体チップの電極と前記第１及び第
２の内部リードとの間を接続する金属細線とを有するこ
とを特徴とする半導体装置。a ceramic container in which an element mounting portion is provided on the bottom surface of a recess provided in an inner central portion; first internal leads arranged near an inner peripheral edge of an upper horizontal surface of the recess; and the first internal leads. an insulating film provided at least in the middle between the first internal lead and the second internal lead; and a semiconductor chip mounted on the element mounting portion. . A semiconductor device comprising: a thin metal wire connecting between the electrode of the semiconductor chip and the first and second internal leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100417A JPH02278742A (en) | 1989-04-19 | 1989-04-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1100417A JPH02278742A (en) | 1989-04-19 | 1989-04-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02278742A true JPH02278742A (en) | 1990-11-15 |
Family
ID=14273406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1100417A Pending JPH02278742A (en) | 1989-04-19 | 1989-04-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02278742A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
-
1989
- 1989-04-19 JP JP1100417A patent/JPH02278742A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
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