JPH02277142A - Duplex computer system - Google Patents

Abstract

PURPOSE:To substantially assure the continuity when the switch is carried out between the computers of a main system and a spare system by transmitting the data on a certain module and the execution information on all modules to the computer of the spare system when the computer of the main system finishes the execution of the specific module. CONSTITUTION:When a CPU 11 of a main system writes the information in a real work memory 12, the address information and the data information area also sent to an external bus 65. Then these address/data information are inputted to an external memory device 8 of a spare system via a differential amplifier transmission circuit 61 of an external memory device 7 and then reach a saving memory 63 via a differential amplifier reception circuit 62 of the device 8. The data information is written into an address of the memory 63 in response to the address information. The CPU 11 writes the necessary information into the memory 12 when the module to be executed is switched to another. At the same time, the module execution end information showing the end of execution of a module is written into the corresponding area of the memory 63 together with the module execution information showing the run states of said module and all other modules.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a standby redundant dual system computer system that improves the memory transfer function and can more reliably switch computers.

[Conventional technology]

FIG. 7 is a conceptual block diagram of a conventional dual system computer system disclosed in, for example, Japanese Patent Publication No. 1809/1983.

In FIG. 7, la and 2a are computers, 3 is a redundant control device, 41 and 42 are input/output buses of the computers 1a and 2a, respectively, 5 is an input/output bus switch, and 6 is an input/output device.

The redundant control device 3 is connected to the two computers 1a and 2a through a memory bus, a supervisory signal line, a control signal line, etc., and performs operation monitoring of the double-handled calculator, human output bus usage permission control, and memory transfer control. The duplex control device 3 also provides a control signal to the input/output bus switch 5 to control its switching.
211.

Redundant control device i! 3 determines the status of the two computers 1a and 2a, gives a human output bus use permission signal to one of the normal computers, and turns on the input/output bus switch 5 to that side. Of the two computers la and 2a, the one to which the input/output bus usage permission signal is applied engages in actual work, while the other computer stands by.

The detailed connection relationship between the computers 1a, 2a and the duplex control device 3 is shown in FIG. 8, focusing on the memory transfer means. However, in Figure 8, in order to avoid y1 complexity, the computer 1
This figure shows only the configuration of the memory transfer system from computer 1a to computer 2a when a is on the actual work side and computer 2a is on the standby side, and the memory transfer system from computer 2a to computer 1a is exactly the same. It is configured. Calculator 1a, 2
a are processor 11, 21 and main memory 12, respectively.
I have ゜22. The duplication control device 3 includes an address monitor section 31 having a first-in/first-out memory (FIFO), a monitoring section 32, a database equalization section 33, a database copying section 34, and a FIFO in the address monitor section 31. It has a detection section 35 that detects an overflow.

The address monitor section 31 intercepts the address when the computer 1a accesses the memory, and when it receives the address accompanied by the equalization request signal, stores it in the FIFO. The monitoring section 32 monitors the ready signals of the computers 1a and 2a and the data ready signal of the address monitoring section 31, and controls the operations of the database equalization section 33 and the database copying section 34. The database equalizer 33 reads the main memory of the computer 1a according to the control signal of the monitor 32 and the address given from the FIFO of the address monitor 31, and writes the read data to the same address in the main memory of the computer 2a. As a result, the data requested by the computer 1a is transferred to the computer 2a and equalized. FIF
O buffers the timing difference between the memory access of the computer 1a and the equalization operation of the duplex control device 3. The equalization request by the computer 1a is issued when the computer 1a writes certain data in the database in the main memory 12. This type of data is commonly used when the computers 1a+2a perform actual work. Therefore, each time this kind of shared data changes due to the depression of computer 2a, the changed data is transferred to the database of computer 2a. On the other hand, the database copying section 34 writes the entire database of the computer la to the computer 2a according to the control signal from the monitoring section 32.

The operation of the database copying section 34 is mainly performed by the computer 2a.
This is performed as one of the initialization tasks for the computer 2a after it is input into the dual system. The database equalization section 33 and the database copying section 34 can operate in parallel. Therefore, when the computer 1a rewrites shared data during database copying, equalization is performed for each piece of data.

The FIFO overflow detection section 35 detects that a new equalization request has occurred in the FIFO of the address monitor section 31 in a state where the addresses to be equalized according to the previously generated equalization request have been satisfied ( FIFO overflow).

On average, the operation speed of the database equalization unit is sufficiently faster than the frequency of equalization requests of computer 1a, but momentarily, the frequency of equalization requests exceeds the processing speed of equalization operations. In this case, FIFO acts as a buffer. There is no problem if the FIFO capacity is sufficient, but in reality it is limited, so when the frequency of equalization requests becomes extremely high, the above FIFO
FO overflow may occur. When the PIF-0 overflow detection unit 35 detects this state, the PIF-0 overflow detection unit 35 immediately detects this condition.
Notify 2. Once the monitoring unit 32 learns of this, it immediately
After resetting the FO and initializing it to an empty state, the database copying section 34 is activated to copy all the data in the computer 1a to the computer 2a.

This ensures matching even for addresses that cannot be equalized due to FIFO overflow. In this operation as well, the database equalization section 33 starts operating again at the same time as the database copying section 34 is activated, and operates in parallel with the entire database transcription.

[Problem to be solved by the invention]

Since the conventional dual-system computer system is configured as described above, even if the contents of the main memories 12 and 22 provided in the dual-hand calculators 1a and 2a match, the computer 1
It is difficult to strictly maintain the continuity of program execution when switching between a and 2a, and there are problems such as the need for means to prevent missing or duplicate execution of instructions at the switching point. Furthermore, when the running computer 1a processes multi-tasks (multiple modules) in parallel in a time-sharing manner, in order to avoid the difficulty of maintaining continuity at the switching point, the task is executed immediately before the switching occurs. When the other computer 2a executes the module from the beginning of the module, the period from the beginning of the module to the switching point may have been executed once, and the data to be handled may have changed. There were issues such as the fact that the processing results would not be accurate if the process was executed.

This invention was made to solve the above-mentioned problems, and it ensures substantial continuity by executing from the beginning of the module when switching computers, and also,
To obtain a dual-system computer system in which processing of a module is performed without contradiction even when the module is executed from the beginning, and subsequent task switching can be performed without any problem.

[Means to solve the problem]

The dual computer system according to the invention described in claim (1) has an external memory device corresponding to each computer,
These external memory devices include a backup memory with a capacity at least equal to the memory capacity of the actual working memory in the computer, and a first memory device that outputs data on the bus of the connected computer to the other external memory device via a buffer. an interface circuit; and a second interface circuit that becomes operable alternatively to the first interface circuit and supplies data supplied from the other external memory device to the save memory via a buffer; When each calculator is on standby,
Detects the module execution completion information of a certain module output by the other computer, imports the module execution information and updated data regarding the module that has finished execution from the save memory of the connected external memory device, and executes the own actual work. The module information transfer means is configured to transfer the information to the memory.

Further, the dual computer system according to the invention described in claim (2) has an external memory device corresponding to each computer, and these external memory devices temporarily store data output from the connected computers. It has a save memory to save, and a microprocessor sensor that detects module execution completion information present in the output data and controls the transfer of the data in the save memory to the other external memory device,
During operation, when each computer writes updated data to the actual working memory within the computer, it outputs this updated data along with an address to a connected external memory device, and
A module information output means outputs module execution information including module execution completion information when the module execution ends, and when on standby, it takes in data from the save memory of a connected external memory device and stores updated data and data in its own actual working memory. and module information transfer means for transferring module execution information.

[For production]

The external memory device according to the invention described in claim 11 introduces a computer bus, and when the computer updates data at a certain address in the actual working memory, the data on the bus is saved in another external memory device. Then, the other computer, that is, the standby computer, recognizes that the running computer has finished executing a certain module and saves the external memory device connected to the standby computer. Data regarding the executed module and module execution information are introduced from the memory and transferred to its own actual working memory.

Further, the external memory device according to the invention described in claim (2) introduces the update data and its address outputted by the operating computer, stores it in the save memory, and terminates the execution of the module with the operating computer. It detects that the module has been executed, and sends data regarding the module that has completed execution, its address, and module execution information to the other external memory device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, numbers 7 and 8 each represent a total of 1X machines.

2 is an external memory device connected to 2, 65a is a bus (address bus and data bus), 65b is a control signal (including operation commands and abnormal signals), and the other parts are denoted by the same reference numerals as shown in FIG. It is the same as shown. FIG. 2 is a block diagram (first
example). In the figure, 11.21 is the central processing unit (CPU) of computers 1 and 2, respectively, 12.22 is the actual working memory of computer 1.2, and 61 is the address and data on the external bus 65 that is transferred to the other external memory device. 7. Differential amplifier transmitter circuit (first
62 is a differential amplifier receiving circuit (second interface circuit) that receives the address and data given from the other external memory device 7.8.
3 is a backup memory with the same capacity as the actual working memory 12.22,
65 is an external bus including a bus 65a and a control signal 65b, and 77 and 78 are duplex execution determination circuits. In addition,
Differential amplifier transmitting circuit 61 and differential amplifier receiving circuit 62
As shown in FIG. 3, through two switch circuits 64a and 64b whose 0N10FF states are reversed,
Only one of them will be connected to computer 1.2. The switch circuits 64a, 64b can be switched manually. Note that both external memory devices 7.8 have the configuration shown in FIG. 3, but in FIG. 2, each external memory device 7.8 only shows one differential amplifier. In the following description, the computer 1 is assumed to be the operating side (main system), and the calculation a2 is assumed to be the standby system.

Next, the operation will be explained. The external memory device 78 monitors the operation of the recomputer 1.2 and controls permission to use the input/output bus as in the conventional case. In other words, the duplication execution determination circuit 7
7. On the 7th, the status of both needle amounts a12 is determined, and an input/output bus use permission signal is given to one of the normal computers l.
In addition, the input/output bus switch 5 is placed on that side. Therefore, the computer 1 becomes the main system, and the other computer 2 becomes the standby system.

Next, transfer control of data and module execution information will be explained. When the main CPU II performs a write operation to the actual working memory 12, address information and data information also flow to the external bus 65. This address/take information is manually input to the standby external memory device 8 via the differential amplifier transmission circuit 61 of the external memory device 7. The signal then reaches the save memory 63 via the differential amplifier receiving circuit 62 of the external memory device 8 . In the save memory 63, data information is written to an address corresponding to the address information.

When switching the module to be executed, the main CPU II writes necessary information to the actual working memory 12, so at the same time, a module indicating that the execution of the module has been completed is written in the corresponding area of the save memory 63 of the external memory device 8. Execution end information and module execution information indicating the seven wheel running status of this module and all other modules are written.

Here, the main CPU 1 may be configured to receive responses from both the actual working memory 12 and the external memory device 8. The external memory device 8 issues an interrupt request to the standby CPU 21 in response to the module execution completion information being written to the save memo IJ63. The standby CPU 21 transfers necessary data and module execution information from the save memory 63 of the external memory device 8 to the actual working memory 22 in response to this interrupt request. Here, the standby CPU 21 and the program in the computer 2 implement module information transfer means. for example,
The standby CPU 21 checks the source address table of the module corresponding to the module execution completion information, and takes in the data of the address registered in this source address table from the save memory 63. here,
A source address table provided for each module is configured to point to addresses where data used by each module is stored. Note that the save memory 63 has a two-port memory configuration. Also, the reason why the external memory devices 7 and 8 are interfaced by a differential amplifier is that if one of the external memory devices 8 fails,
When the standby system calculation 412 is powered off, the backup memory 6 provided in the other external memory device 7
This is to prevent the contents of 3 from being destroyed.

Note that the external memory device 7.8 outputs equalization request signals 79a and 79b when the power of the standby computer 2 is turned off and then turned on again, or when initialization is performed. Upon receiving the equalization request signals 79a and 79b, the main CPU 1 reads out the contents of the entire area of the actual working memory 12 and outputs them to the external bus 65. Therefore, the contents of the actual working memory 12 of the main system calculation if are transferred to the save memory 63 of the external memory device 8. Further, the standby CPU 21 transfers the contents of the save memory 63 to the actual working memory 22. This allows the actual working memory 12.
The sameness of content between 22 is ensured.

Further, in the above embodiment, the operation monitoring of the recomputer 1.2 is performed on the external memory device 7.8, but it may be realized by independent hardware.

Then, the external memory device 8 detects the module execution end information and issues an interrupt request to the standby computer 2, but the standby computer 2 uses the corresponding area of the save memory 63 of the external memory device 8. A polling configuration may also be used.

Further, the source address table provided corresponding to the module may be provided in the save memory 63, or
It may be provided in the memory within the standby computer 2.

Alternatively, instead of the switch circuits 64a and 64b, the two differential amplifier circuits 61 and 62 may be configured to be automatically enabled/disabled based on the determination result of the duplication execution determination circuit 77.18. good.

FIG. 4 is a block diagram showing the configuration of the calculation al, 2 and external memory device 7.8 of the dual computer system according to the second embodiment of the present invention. In the figure, 71 and 72 are microprocessors (μ-P) provided in the external memory device 7.8, 73 and 74 are selectors that select the data transfer direction, and 75 and 76 are temporary savers for data. Memory, 77.78 is a duplication execution determination circuit,
79a and 79b are equalization request signals. Other parts are designated by the same reference numerals and are the same as those shown in FIG.

Next, the operation will be explained. The external memory device 7.8 monitors the operation of the computer 1.2 and controls the use of the input/output bus as in the previous embodiment.

Next, the transfer control of data and module execution information will be described with computer 1 as the main system and computer 2 as the standby system. The main CPLJII writes data to the actual working memory 12, and writes data/address information indicating the data and the address where the data is stored to the save memory 75 via the selector 73. When the execution of a certain module is completed, the module execution information of all the modules including the module execution completion information of that module is further written to the save memory 75. Here, the main CPU
Module information output means is realized by I and the program of computer I. Moreover, the state of storage in the save memory 75 is shown in FIG. In the example shown in FIG. 5, the area includes a module number 81 of the module being executed, the number of stored data 82, data/address information 83, and module execution information 84. When μmP 71 checks module execution information 84 and detects the completion of execution of any module, it transfers the data/address information and module execution information regarding that module in save memory 75 to an external memory device through selectors 73 and 74. Transfer it to the save memo IJ76 of 8. Then, the standby CPU 21 uses the save memory 76 via the selector 74.
data/address information is input, and based on this information, data is written to the corresponding address in the actual working memory 22 of the standby computer 2. Here, standby cPU2
A module information transfer means is realized by the program 1 and Calculation Ja2. As described above, the data related to the module whose execution has ended and the latest module execution information are also updated in the actual working memory 22 of the standby computer 2. In addition, in the case of initialization, etc., it is the first thing to establish the identity between both actual working memories 12.22, triggered by the equalization request signals 79a and 79b.
This is the same as in the embodiment. However, in the case of this embodiment, the capacity of the save memory 75 and 76 is the actual working memory 12.
．． It may be smaller than the capacity of 22, so the backup memory 7
5.76 is used multiple times to complete the equalization.

In the above embodiment, μmP71 saves the contents of the save memory 75 of the main external memory device 7 to the save memory 76 of the other side.
Although the p-PI 3 of the standby external memory device 8 may perform the transfer, the same effect can be obtained.

Further, as in the case of the first embodiment, the operation monitoring of the recomputer 1.2 can be configured with independent hardware.

FIGS. 6A to 6C are explanatory diagrams showing how two modules (module A and module B) are executed on the main computer l. Figure 6 (A) shows that while module A is being executed, an operation request for module B, which has a higher priority, occurs, and the execution of module A is interrupted (W
AIT state), indicating that module B is executed. It also indicates that after the execution of module B is completed, execution of the module will be resumed.

In the figure, the execution start point of the module is shown as "S", and the execution end point is shown as "EJ".
This is a representation of what was shown in A) with the time axis corrected. Figure 6 (C
).

For example, if an abnormality occurs at point a, it is difficult for computer 2 to continue executing module A accurately from point a, as described above. Just execute from the beginning of module A, that is,
Looking at the module status shown in FIG. 6(C), both module A and module B are in the pre-5TART state, but in the first and second embodiments, module A is running. Since the information is present in the module execution information, the computer 2 can immediately recognize that it only needs to execute from the beginning of the module. Furthermore, the data of module A is stored in the 5TA of module A in the save memory 63 in the first embodiment and also in the save memories 75 and 76 in the second embodiment.
It remains in the pre-RT state, and therefore has not been updated in the actual working memory 22 of the computer 2. In other words, unlike the conventional case, the computer l from the beginning of module A to point a
The data updated in the actual working memory 12 of the computer 2 does not affect the actual working memory 22 of the computer 2. Therefore, even if the computer 2 executes the module from the beginning, there will be no inconsistency in the results.

〔Effect of the invention〕

As described above, according to the present invention, in a dual-system computer system, when the main computer finishes executing a certain module, data regarding that module and module execution information of all modules are transferred to the standby computer. Since the configuration is configured so that the information is transmitted, there is an effect that continuity can be substantially guaranteed when switching computers.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a dual system computer system according to an embodiment of the invention, FIG. 2 is a block diagram showing the structure of a computer and an external memory device in the first embodiment of the invention, and FIG. FIG. 2 is a block diagram showing the detailed configuration of the external memory device shown in FIG. 6(A) to 6(C) are explanatory diagrams illustrating the execution states of modules. FIG. 7 is a configuration diagram illustrating a conventional dual-system computer system. FIG. 8 is a block diagram showing the configuration of the computer and duplex control device shown in FIG. 7. 1 and 2 are computers having module information transfer means or module information transfer means and module information output means; 7 and 8 are external memory devices; 61 is a differential amplifier transmission circuit (first interface circuit); and 62 is a differential amplifier. Receiving circuit (second interface circuit), 63.75 7
6 is a save memory, 71.72 is a microprocessor (μ
-P). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A standby redundant dual system system that includes two computers that share an input/output device and a dual system control means that has a duplex execution determination circuit that monitors the operations of these computers and operates one of the computers. In the multiple computer system, the dual system control means is composed of two external memory devices each connected to one of the computers, and each of the external memory devices stores the actual working memory of each computer. a save memory having at least the same capacity as the memory capacity; a first interface circuit that outputs data on the bus of the connected computer to the other external memory device via a buffer; a second interface circuit that becomes operable alternatively to the interface circuit and supplies data supplied from the other external memory device to the save memory via a buffer; Detects the module execution completion information of a certain module output by the other computer, imports the module execution information and updated data regarding the module from the save memory of the connected external memory device, and stores it in its own actual working memory. A dual-system computer system characterized by having a module information transfer means for transferring module information to a computer. (2) A standby redundant dual system system that includes two computers that share an input/output device and a dual system control means that has a duplex execution determination circuit that monitors the operations of these computers and operates one of the computers. In the multiple computer system, the dual system control means is composed of two external memory devices each connected to one of the computers, and each of the external memory devices stores information output from the connected computers. Each computer includes a save memory that temporarily saves data, and a microprocessor that detects module execution completion information present in the data and transfers the data in the save memory to the other external memory device, During operation, when writing updated data to the actual working memory in the computer, this updated data is output to the connected external memory device along with the address, and when the execution of a certain module ends, the execution of the module is terminated. module information output means for outputting module execution information including information; and a module information output means for outputting module execution information including information;
module information transfer means for capturing data from the save memory of the connected external memory device and transferring the update data and module execution information to its own actual working memory based on the address in the data; A dual system computer system characterized by: