JPH02276269A - Semiconductor device - Google Patents

Abstract

PURPOSE:To relax stress occurred at the brazing of a chip to prevent a device of this design from lessening in manufacturing yield and reliability by a method wherein a capacitive structure is not formed above a viahole where stress occurs, and only a lower electrode is left to enable a grounding connection to be made. CONSTITUTION:A capacitor lower electrode 2, a dielectric film 3, and a capacitor upper electrode 4 are successively formed on a substrate 1, where the lower electrode 2 of a component part of a capacitor is connected to a grounding conductive layer 6 formed inside a viahole 5 and the rear side of the substrate 1. The dielectric film 3 and the capacitor upper electrode 4 are constituted in such a pattern that they are not provided above the viahole 5.

Description

[Detailed Description of the Invention] (Summary) The grounding structure of a capacitor in a semiconductor device, especially an MMIC (
Monolithic Microwave IC) MIM (Metal Insulator Metal
) Concerning the grounding structure of structural capacitors.

The purpose of this project is to obtain a mechanically stress-free capacitor grounding structure using the via hole method, which has the characteristics of low grounding inductance and small footprint.

A lower electrode and a dielectric film are laminated in this order on a substrate.

It has a capacitor constituted by an upper electrode, and a ground conductive layer connected to a ground potential below the substrate.

The substrate has a through hole formed under the capacitor.

The lower electrode is electrically connected to the ground conductive layer through the through hole, and the dielectric film and the upper electrode are formed in a pattern in which a portion corresponding to the through hole is omitted.

[Industrial application field]

The present invention relates to a grounding structure for a capacitor in a semiconductor device.

In particular, it relates to the grounding structure of a 11C MIM structure capacitor.

Parallel plate capacitors with an MIM structure are often used in MMICs using semi-insulating (Sl-) GaAs substrates.

The present invention can be used as a low inductance, high frequency grounding structure for capacitors of MIM structure.

[Conventional technology]

MMI using a 1, for example, 5r-GaAs substrate as a substrate
In C, MIM structure capacitors are used everywhere.

Many of these capacitors have one side grounded by one circuit.

In this case, the high frequency grounding structure may be a primary one.

(2) Ultra-fine wire bonding method (or ribbon bonding method) FIG. 2 is a plan view illustrating a grounding structure using ultra-fine wire bonding.

In the figure, capacitor lower electrodes 2. Dielectric smell 3. In this structure, a capacitor upper electrode 4 is formed, and a ground (GND) plane formed under the substrate and the lower electrode 2 are bonded with a very thin wire 7.

(2) Via Hole Method This is a method in which a via hole is formed through the 5r-GaAs substrate, and conduction is established through this hole to provide grounding.

FIG. 3 is a sectional view illustrating a via hole type grounding structure.

In the figure, capacitor lower electrodes 2. Dielectric film 3. A capacitor upper electrode 4 is formed, and the lower electrode 2 is a part extending from the capacitor part, and is connected to a ground conductive layer (
(ground plane) 6.

In the μ wave band or 111111 wave band, the ground inductance L(i
It is desirable that ND be as small as possible in order to obtain circuit stability and high gain. For example, in the 2 GHz band.

. <1 nH is required.

For this reason and because of the flexibility of placement, the via hole method is often used.

The via hole method provides a low ground inductance of LGND < 0.1 nH.

However, in the frequency band above 10 Gllz, a smaller grounding inductance was required, and in order to reduce the area occupied by the capacitor, the structure shown in Fig. 4 was modified from Fig. 3 and began to be used. .

FIG. 4 is a diagram of a conventional example, and is a sectional view illustrating an improved via hole type grounding structure.

In Fig. 3, the via hole is provided outside the capacitor, whereas in the structure shown in Fig. 4, the via hole is provided directly below the capacitor.
The area occupied by the capacitor arrangement is reduced.

[Problem to be solved by the invention]

However, a chip with such a structure, A
When bonding to the stage using a brazing material such as uSn or AuGe, the ground conductive layer (gold or silver plating) 6 in the via hole melts with the brazing material.

Mechanical stress is generated during solidification, causing the capacitor to bulge or dent, deforming it.

It has been found that cracks occur in the dielectric (si3N4. or 5i(h) layer) and metal penetrates into the cracks, causing a short circuit in the capacitor or a short circuit during operation.

An object of the present invention is to obtain a mechanically stress-free capacitor grounding structure using a via hole method, which has the characteristics of low grounding inductance and small occupied area.

(Means for solving the problem) The solution to the above problem is to
It has a capacitor composed of a dielectric film and an upper electrode, and a ground conductive layer connected to a ground potential on the lower side of the substrate, and the substrate has a through hole formed on the lower side of the capacitor and The electrode is electrically connected to the ground conductive layer through the through hole, and the dielectric film and the upper electrode are realized by a semiconductor device formed in a pattern in which a portion corresponding to the through hole is omitted.

[Effect]

The present invention does not form a capacitor structure in the upper part of the via hole where stress occurs, leaving only the lower electrode to enable ground connection, thereby alleviating stress during chip brazing and improving manufacturing yield. This is to prevent a decrease in the reliability of the device and a decrease in the reliability of the device.

(Embodiment) FIGS. 1(1) and 1(2) are a sectional view and a plan view illustrating a via hole type grounding structure according to an embodiment of the present invention.

In the figure, on a 5l-GaAs substrate 1 with a thickness of 75 μm! lli order capacitor lower electrode 2. Dielectric film 3. A capacitor upper electrode 4 is formed, and the lower electrode 2 is connected at the capacitor portion to a ground conductive layer 6 formed within the via hole 5 and on the back surface of the substrate.

Dielectric film 3. The capacitor upper electrode 4 is formed in a hollow pattern above the via hole 5 .

Here, the capacitor is The lower electrode 2 is an AuGeNiAu film with a thickness of 0.3 μm.

The dielectric film 3 is composed of a Si3N4 film 5 with a thickness of 0.2 μm, and the upper electrode 4 is composed of an Au plating film with a thickness of 2 μm.

Further, the ground conductive layer 6 is formed of an Au plating film with a thickness of 15 μm.

As mentioned above, the points that must be considered in the capacitor grounding structure can be summarized as follows.

■ Capacitors should have low ground inductance and low series resistance.

■ Flexibility in placement of capacitors on the chip.

■ The area occupied by the capacitor arrangement is small.

In this example, the above-mentioned considerations (1) and (2) have values intermediate between those of the structures of FIGS. 3 and 4, but will not cause a fatal defect that short-circuits the capacitor.

When the chips were brazed using AuSn as the brazing material, no total heat was generated due to capacitor short circuits in many samples. Therefore, it was confirmed that this method is effective in improving the manufacturing yield and the reliability of the device. Furthermore, the ground inductance was as low as 0.05 nll.

FIGS. 5(1) and 5(2) are a plan view and a circuit diagram showing an example of an M old C to which the present invention is applied.

This MMIC has a 1-8 GHz wide band with 2 additional frequencies (gain #8 dll) and a chip size of 1.3 mm x 1.
．． The present invention is applied to capacitors C2+C4, which are formed on a 7 mm 5R-GaAs substrate.

GaAs MES FET nll q, the channel region is formed by ion implantation, and the resistance R is also 54-GaAs
Ions are implanted into the substrate to form a resistor. The rectangle in the circuit diagram represents a microstrip line.

Capacitor C2 has one via hole, capacitor C4 has two
It is connected to the ground terminal VCC via the via holes 5.

〔Effect of the invention〕

As described above, according to the present invention, a mechanically stress-free capacitor grounding structure can be obtained using the via hole method, which is characterized by low grounding inductance and small occupied area.

Therefore, the manufacturing yield and reliability of MMIC can be improved.

[Brief explanation of drawings]

FIGS. 1 (1) and (2) are a sectional view and a plan view illustrating a via hole type grounding structure according to an embodiment of the present invention. FIG. 2 is a plan view illustrating a grounding structure using ultrafine wire bonding. FIG. 3 is a sectional view illustrating a via hole type grounding structure. FIG. 4 is a diagram of a conventional example, and is a sectional view illustrating an improved via hole type grounding structure. FIGS. 5(1) and 5(2) are a plan view and a circuit diagram showing an example of an MMIC to which the present invention is applied. In fig. l is the substrate, which is a 5I-GaAs substrate. 2 is the capacitor lower electrode. 3 is a dielectric film. 4 is the upper electrode of the capacitor. 5 is a via hole. 6 is the grounding structure where the grounding groove is layered with the wire 1ζJ.

Claims (1)

[Claims] A capacitor comprising a lower electrode, a dielectric film, and an upper electrode stacked in order on a substrate, and a ground conductive layer connected to a ground potential below the substrate, A through hole is formed in the substrate below the capacitor, the lower electrode is electrically connected to the ground conductive layer through the through hole, and a portion of the dielectric film and the upper electrode corresponds to the through hole. A semiconductor device characterized in that it is formed in a missing pattern.