[go: up one dir, main page]

JPH02275417A - Thin film transistor for display element - Google Patents

Thin film transistor for display element

Info

Publication number
JPH02275417A
JPH02275417A JP1097949A JP9794989A JPH02275417A JP H02275417 A JPH02275417 A JP H02275417A JP 1097949 A JP1097949 A JP 1097949A JP 9794989 A JP9794989 A JP 9794989A JP H02275417 A JPH02275417 A JP H02275417A
Authority
JP
Japan
Prior art keywords
display electrode
insulating film
gate
electrode
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1097949A
Other languages
Japanese (ja)
Inventor
Osamu Sukegawa
統 助川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1097949A priority Critical patent/JPH02275417A/en
Publication of JPH02275417A publication Critical patent/JPH02275417A/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent a display electrode from defective short-circuiting even if a pattern defect is generated and to improve the yield by forming an insulating film after a gate electrode is formed, then forming a display electrode and a gate insulating film, and coupling the display electrode with the source electrode of the thin film transistor(TFT) through through-hole wiring with drain wiring metal. CONSTITUTION:The insulating film 3 is formed on the gate electrode 2, the display electrode 4 is formed on it, and the gate insulating film 5 and a semiconductor layer 6 are further formed thereupon. The display electrode 4 and TFT 8 are connected electrically to each other through a through hole 9 formed in the gate insulating film 5. Namely, the display electrode 4 and gate 2 are separated by an SiO2 film 3 and the display electrode 4 and drain 7 are separated by a silicon nitride film which is the gate insulating film 5. Consequently, electrical short-circuiting never generated between the display electrode 4 and drain 7, and the short-circuiting defect can be eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、アクティブマトリクスデイスプレィに用いら
れる薄膜トランジスタに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor used in an active matrix display.

〔従来の技術〕[Conventional technology]

従来、この種の表示素子用薄膜トランジスタは、第4図
の平面図および第4図のB−B断面図である第5図に示
すように、表示電極4はドレイン7と同一面内に形成さ
れた構造とされていた。
Conventionally, in this type of thin film transistor for a display element, the display electrode 4 is formed in the same plane as the drain 7, as shown in FIG. 5, which is a plan view of FIG. 4 and a BB cross-sectional view of FIG. It was said to have a similar structure.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の表示素子用薄膜トランジスタは、ドレイ
ンと表示電極が同一面上に形成されるため、いずれかの
パターン欠陥により表示電極は、トレインと電気的に短
絡し、素子欠陥となる欠点がある。この素子欠陥は、デ
イスプレィ表示において表示不良点となる。一般に表示
電極とビレ。インパターンのスペースを広くとれば、こ
のような短絡欠陥は減少するが、デイスプレィにおいて
は画面輝度を大きくするため、表示電極はできる限り広
くとることが望ましく、このことは上述した短絡欠陥を
増大させてしまう。
In the conventional thin film transistor for a display element described above, since the drain and the display electrode are formed on the same surface, any pattern defect causes the display electrode to be electrically shorted to the train, resulting in an element defect. This element defect becomes a display defect in a display. Generally display electrode and fin. If the in-pattern space is widened, such short circuit defects will be reduced, but in order to increase the screen brightness in a display, it is desirable to make the display electrode as wide as possible, which increases the short circuit defects mentioned above. It ends up.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の表示素子用薄膜トランジスタは、ゲート電極上
に絶縁膜を形成し、その上に表示電極を形成し、その上
にゲート絶縁膜と半導体層を形成した構造を有している
。なお、表示電極と薄膜トランジスタは、ゲート絶縁膜
に設けたスルーホールを介して電気的に接続される。
The thin film transistor for a display element of the present invention has a structure in which an insulating film is formed on a gate electrode, a display electrode is formed on the insulating film, and a gate insulating film and a semiconductor layer are formed on the insulating film. Note that the display electrode and the thin film transistor are electrically connected through a through hole provided in the gate insulating film.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
は、本発明の第1の実施例の平面図であり、第2図は、
第1図のA−A断面図である。
Next, the present invention will be explained with reference to the drawings. FIG. 1 is a plan view of the first embodiment of the present invention, and FIG.
FIG. 2 is a sectional view taken along line A-A in FIG. 1;

本実施例の薄膜トランジスタは、表示電極4とゲート2
は5i02膜3によって分離されており、又、表示電極
4とドレイン7はゲート絶縁膜5である窒化シリコン膜
によって分離された構造を有している。
The thin film transistor of this embodiment has a display electrode 4 and a gate 2.
are separated by a 5i02 film 3, and the display electrode 4 and drain 7 are separated by a silicon nitride film, which is a gate insulating film 5.

本実施例の薄膜トランジスタは、以下の工程により形成
される。ガラス基板1上にスパッタによりCrを140
nm成膜し、パターン化することによりゲート2を形成
する。その上にスパッタもしくはプラズマCVDにより
SiO□膜3を1100n形成した後、透明導電体であ
るITO(Indium Tin 0xide)をスパ
ッタにより50膜m成膜し、ITOをパターン化するこ
とにより表示電極4を形成する。この後、薄膜トランジ
スタのゲート絶縁膜5としてSiNxを300nmプラ
ズマCVD法によって成膜し、さらにその上にアモルフ
ァスシリコン層(a−Sill)6を800nm形成し
トランジスタ部以外のa−Si層をエツチング除去し、
表示電極上のSiNx膜をエツチングしてスルーホール
9を形成する。なお、a−Si層6は動作層であるN−
a−3i層300nmとオーミックコンタクト層である
n”−a−3i層500nmからなる。このa−3i層
およびSiNx膜のエツチングは、通常CF4もしくは
CF、に02を混合したガス系によるドライエツチング
法が用いられる。この後、スパッタ法により、Crを2
00nm成膜しパターン化することによりドレイン7及
びソース8を形成する。ソース8は、スルーホール9を
介して表示電極4と電気的に結合される。最後にトレイ
ン7およびソース8間のn+−a−Siをエツチング除
去することにより、薄膜トランジスタが完成する。この
ような構造のため、表示電極とドレインとが電気的に短
絡することが全くない。
The thin film transistor of this example is formed by the following steps. 140% Cr is deposited on the glass substrate 1 by sputtering.
A gate 2 is formed by depositing a film of nm thickness and patterning it. After forming 1100 nm of SiO □ film 3 on it by sputtering or plasma CVD, 50 m of ITO (Indium Tin Oxide), which is a transparent conductor, is formed by sputtering, and the display electrode 4 is formed by patterning the ITO. Form. Thereafter, a 300 nm SiNx film was formed by plasma CVD as the gate insulating film 5 of the thin film transistor, and an 800 nm amorphous silicon layer (a-Sill) 6 was formed on top of it, and the a-Si layer other than the transistor part was removed by etching. ,
Through holes 9 are formed by etching the SiNx film on the display electrodes. Note that the a-Si layer 6 is an active layer of N-
It consists of a 300 nm thick a-3i layer and a 500 nm n''-a-3i layer which is an ohmic contact layer.The a-3i layer and SiNx film are usually etched using a dry etching method using a gas system containing CF4 or CF mixed with 02. After that, 2 Cr is added by sputtering.
A drain 7 and a source 8 are formed by forming a film with a thickness of 00 nm and patterning it. Source 8 is electrically coupled to display electrode 4 via through hole 9 . Finally, the n+-a-Si between the train 7 and the source 8 is removed by etching to complete the thin film transistor. Due to this structure, there is no electrical short circuit between the display electrode and the drain.

第3図は、本発明の第2の実施例の縦断面図である。ゲ
ート2は厚さ300nmのTaで形成され、ゲートパタ
ーン形成後、陽極酸化処理を行なうことによりゲート2
の表面に絶縁体であるTa205膜10が形成される。
FIG. 3 is a longitudinal sectional view of a second embodiment of the invention. The gate 2 is formed of Ta with a thickness of 300 nm, and after the gate pattern is formed, the gate 2 is formed by anodizing.
A Ta205 film 10, which is an insulator, is formed on the surface.

この後、透明導電膜を成膜しパターン欠陥グすることに
より表示電極4を形成し、あとは第1の実施例と同様の
成膜・PRエッチング工程をへることにより薄膜トラン
ジスタが形成される。
Thereafter, a display electrode 4 is formed by forming a transparent conductive film and removing pattern defects, and a thin film transistor is formed by performing the same film forming and PR etching steps as in the first embodiment.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ゲート電極を形成した後
に絶縁膜を形成し、その後、表示電極を形成し、その後
ゲート絶縁膜を形成し、ドレイン配線メタルにより表示
電極と薄膜トランジスタのソース電極をスルーホール配
線により結合することにより、表示電極は、ゲート及び
トレイン配線と絶縁膜によって分離されるため、各配線
層及び表示電極のパターン欠陥が発生しても表示電極の
短絡不良とはならず、薄膜トランジスタアレイの歩留り
が大幅に向上する効果がある。
As explained above, the present invention forms an insulating film after forming a gate electrode, then forms a display electrode, then forms a gate insulating film, and connects the display electrode and the source electrode of the thin film transistor through the drain wiring metal. By connecting through the hole wiring, the display electrode is separated from the gate and train wiring by the insulating film, so even if a pattern defect occurs in each wiring layer or display electrode, it will not cause a short circuit failure in the display electrode, and the thin film transistor This has the effect of significantly improving the yield of arrays.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の第1の実施例の平面図、第2図は、
第1図のA−A断面図、第3図は、本発明の第2の実施
例の縦断面図、第4図は、従来の薄膜トランジスタの平
面図、第5図は、第4図のB−B断面図である。 1・・・ガラス基板、2・・・ゲート、3・・・SiC
2膜、4・・・表示電極、5・・・ゲート絶縁膜、6・
・・アモルファスシリコン層、7・・・ドレイン、8・
・・ソース、9・・・スルーホール、10・・・Ta2
05膜。
FIG. 1 is a plan view of the first embodiment of the present invention, and FIG. 2 is a plan view of the first embodiment of the present invention.
1, FIG. 3 is a longitudinal sectional view of the second embodiment of the present invention, FIG. 4 is a plan view of a conventional thin film transistor, and FIG. 5 is B in FIG. -B sectional view. 1... Glass substrate, 2... Gate, 3... SiC
2 film, 4... display electrode, 5... gate insulating film, 6...
...Amorphous silicon layer, 7...Drain, 8.
...Source, 9...Through hole, 10...Ta2
05 membrane.

Claims (1)

【特許請求の範囲】 1、逆スタガード構造を有する表示素子用薄膜トランジ
スタにおいて、ゲート電極の上に絶縁膜を成膜し、その
上に表示電極を形成し、その上にゲート絶縁膜、半導体
層を形成することを特徴とする表示素子用薄膜トランジ
スタ。 2、表示電極と薄膜トランジスタは、ゲート絶縁膜に設
けられたスルーホールを介して電気的に結合される請求
項1記載の表示素子用薄膜トランジスタ。
[Claims] 1. In a thin film transistor for a display element having an inverted staggered structure, an insulating film is formed on the gate electrode, a display electrode is formed on it, and a gate insulating film and a semiconductor layer are formed on it. 1. A thin film transistor for a display element, characterized in that: 2. The thin film transistor for a display element according to claim 1, wherein the display electrode and the thin film transistor are electrically coupled via a through hole provided in the gate insulating film.
JP1097949A 1989-04-17 1989-04-17 Thin film transistor for display element Pending JPH02275417A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1097949A JPH02275417A (en) 1989-04-17 1989-04-17 Thin film transistor for display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1097949A JPH02275417A (en) 1989-04-17 1989-04-17 Thin film transistor for display element

Publications (1)

Publication Number Publication Date
JPH02275417A true JPH02275417A (en) 1990-11-09

Family

ID=14205922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1097949A Pending JPH02275417A (en) 1989-04-17 1989-04-17 Thin film transistor for display element

Country Status (1)

Country Link
JP (1) JPH02275417A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0850308A (en) * 1994-06-03 1996-02-20 Furontetsuku:Kk Method of manufacturing electro-optical element
JP2010204656A (en) * 2009-02-27 2010-09-16 Beijing Boe Optoelectronics Technology Co Ltd Tft-lcd array substrate and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61145582A (en) * 1984-12-20 1986-07-03 キヤノン株式会社 Display unit
JPS62119525A (en) * 1985-11-20 1987-05-30 Sanyo Electric Co Ltd Thin film transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61145582A (en) * 1984-12-20 1986-07-03 キヤノン株式会社 Display unit
JPS62119525A (en) * 1985-11-20 1987-05-30 Sanyo Electric Co Ltd Thin film transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0850308A (en) * 1994-06-03 1996-02-20 Furontetsuku:Kk Method of manufacturing electro-optical element
JP2010204656A (en) * 2009-02-27 2010-09-16 Beijing Boe Optoelectronics Technology Co Ltd Tft-lcd array substrate and method of manufacturing the same
US8917365B2 (en) 2009-02-27 2014-12-23 Beijing Boe Optoelectronics Technology Co., Ltd. Method of manufacturing TFT-LCD array substrate

Similar Documents

Publication Publication Date Title
US6562645B2 (en) Method of fabricating fringe field switching mode liquid crystal display
US6383831B2 (en) Methods of forming thin-film transistor display devices
JP2008107849A (en) Liquid crystal display device and manufacturing method thereof
US5995174A (en) Liquid crystal display apparatus with source/drain electrodes and pixel electrode formed by the same material
JPH08236775A (en) Film transistor, and its manufacture
US6559920B1 (en) Liquid crystal display device and method of manufacturing the same
JPH0580650B2 (en)
JPH07122718B2 (en) Liquid crystal display
JPS60261174A (en) matrix array
JPH02275417A (en) Thin film transistor for display element
KR100663288B1 (en) Manufacturing method of thin film transistor liquid crystal display device
JPH08262492A (en) Liquid crystal display device
KR100466392B1 (en) Method for manufacturing fringe field switching liquid crystal display
JPH09179140A (en) Production of liquid crystal display device
JPH02157827A (en) Thin film transistor array device
JPH0568708B2 (en)
KR910002194B1 (en) Active Matrix Liquid Crystal Display
JP2019508739A (en) Array substrate and method of manufacturing the same
JP2594114B2 (en) Method for manufacturing electrode substrate for liquid crystal display panel
JPS61134786A (en) Display unit
JPH09181323A (en) Manufacture of active matrix display device
JPH04360575A (en) Manufacture of display device
JPS63119256A (en) Manufacture of active matrix substrate
JPH0754386B2 (en) Display device
JP2980803B2 (en) Method of forming metal wiring