JPH02274121A - Cmos delay circuit - Google Patents
Cmos delay circuitInfo
- Publication number
- JPH02274121A JPH02274121A JP1097932A JP9793289A JPH02274121A JP H02274121 A JPH02274121 A JP H02274121A JP 1097932 A JP1097932 A JP 1097932A JP 9793289 A JP9793289 A JP 9793289A JP H02274121 A JPH02274121 A JP H02274121A
- Authority
- JP
- Japan
- Prior art keywords
- transfer gates
- delay time
- cmos
- resistance
- delay circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
- 229910001374 Invar Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＣＭＯＳ遅延回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a CMOS delay circuit.
ＭＯ８集積回路の遅延回路は、回路機能に要求されるタ
イミングを実現するものとして、一般にＣＭＯＳトラン
ジスタとＭ ０８キヤパシタといった遅延素子によって
構成されている。The delay circuit of the MO8 integrated circuit is generally constructed of delay elements such as CMOS transistors and M08 capacitors to realize the timing required for the circuit function.
第２図は従来のＣＭＯＳ遅延回路の一例の回路図である
。FIG. 2 is a circuit diagram of an example of a conventional CMOS delay circuit.
入力信号Ｓ１ｆ、受ける入力端子Ｔｌ を入力としたＣ
ＭＯＳインバータ２の出力信号Ｓ２は直列抵抗３とＭＯ
Ｓキャパシタ８との節点Ｎｉ介して次段の（ＪｉＯＳイ
ンバータ９の入力に信号ＳＮを入力しこのＣＭＯＳイン
バータ９の出力信号Ｓｏが出力端子Ｔｏに供給されてい
る。C with the input terminal Tl receiving the input signal S1f as input
The output signal S2 of the MOS inverter 2 is connected to the series resistor 3 and the MO
A signal SN is input to the input of the next stage (JiOS inverter 9) via a node Ni with the S capacitor 8, and the output signal So of this CMOS inverter 9 is supplied to the output terminal To.
この回路の遅延時間τは、ＣＭＯＳインバータ２のチャ
ネル幅、チャネル長、直列抵抗３の値ＲおよびＭＯＳキ
ャパシタ８の容量Ｃによって決定される。The delay time τ of this circuit is determined by the channel width and channel length of the CMOS inverter 2, the value R of the series resistor 3, and the capacitance C of the MOS capacitor 8.
しかし、上述した従来のＣＭＯＳ遅延回路の遅延時間は
、直列抵抗、ＭＯＳキャパシタおよびＣＭＯＳインバー
タによっである一定の決まった値となるので、回路設計
上微妙なタイミングが要求されて、遅延時間の調整が必
要になる場合に、調整が不可能であるという欠点があっ
た。However, the delay time of the above-mentioned conventional CMOS delay circuit has a certain fixed value due to the series resistor, MOS capacitor, and CMOS inverter, so delicate timing is required in circuit design, and delay time adjustment is required. The disadvantage is that it is impossible to make adjustments when necessary.
不発゛明の目的は、簡単でしかも微妙な遅延時間の調整
が可能な遅延回路全提供することにある。The object of the present invention is to provide a complete delay circuit that is simple and capable of finely adjusting the delay time.
本発明のＣＭＯＳ遅延回路は、二つのｃＭｏｓインバー
タの間に直列抵抗とへ４０８キヤパシタの積分回路を有
する（ＪｉＯ８遅延回路において、前記直列抵抗に複数
のトランスファーゲートを並列に設けて構成されている
。The CMOS delay circuit of the present invention has a series resistor and an integrating circuit of 408 capacitors between two cMOS inverters (in the JiO8 delay circuit, a plurality of transfer gates are provided in parallel with the series resistor).
第１図は本発明の一実施例回路図である。 FIG. 1 is a circuit diagram of one embodiment of the present invention.
ＣＭＯＳ遅延回路は、第２図の直列抵抗３に、ｎ個のト
ランスファーゲート４１〜４ｎを並列接続したことが異
る意思外は、従来の遅延回路と同一である。The CMOS delay circuit is the same as the conventional delay circuit, except that n transfer gates 41 to 4n are connected in parallel to the series resistor 3 shown in FIG.
以下に、ＣＭＯＳ遅延回路の動作を具体的に説明する。The operation of the CMOS delay circuit will be specifically explained below.
例えば直列抵抗３の抵抗値およびトランスファーゲート
４１〜４ｏの抵抗値をすべて几とする。For example, the resistance value of the series resistor 3 and the resistance value of the transfer gates 41 to 4o are all set to 击.
全てのトランスファーゲート４１〜４ｎをオフ状態した
場合、すなわち合成抵抗）ｔＴがＨの場合の遅延時間を
τ０とすれば、トランスファーゲートのうちのいずれか
１個だけをオン状態にした場合の信号Ｓ１忙セ呻喝→彎
の遅延時間τｌは（て。／２）となる。If all the transfer gates 41 to 4n are turned off (that is, the combined resistance) tT is H, the delay time is τ0, then the signal S1 when only one of the transfer gates is turned on is The delay time τl for the transition from busy to busy is (te./2).
一般に、ｎ個中ｉ個のトランスファーゲートヲオン状態
にしたときの合成抵抗ＲＴ１は第（１）式に、その時の
遅延時間τ１は第（２）式に表わすことができる。Generally, the combined resistance RT1 when i out of n transfer gates are turned on can be expressed by equation (1), and the delay time τ1 at that time can be expressed by equation (2).
ＲＴｉ＝几（：１／（ｉ＋１）） ・・・・
・・・・・（１）τ１＝Ｒｒｉゝｃ＝ｅＲ（ｔ／（ｉ＋
ｔ））＝Ｔｏ／（ｉ＋１） ・・・・・・・・・
（２）従って、トランスファーゲート４１〜４ｎのオン
の数を制御して遅延時間をよシ微細ステップに調整でき
るという利点がある。RTi=几(:1/(i+1))...
...(1) τ1=Rriゝc=eR(t/(i+
t))=To/(i+1) ・・・・・・・・・
(2) Therefore, there is an advantage that the delay time can be adjusted in finer steps by controlling the number of on-states of the transfer gates 41 to 4n.
なお、トランスファーゲートの各抵抗値が凡の値と異っ
て設定してもよい。Note that each resistance value of the transfer gate may be set to be different from the normal value.
以上説明したように本発明は、遅延時間を決める直列抵
抗に対して並列にあるオン抵抗値を持ったｎ個のトラン
スファーゲートを挿入することにより、遅延時間を要求
される値に調整することが可能となる。As explained above, the present invention makes it possible to adjust the delay time to a required value by inserting n transfer gates with a certain on-resistance value in parallel to the series resistor that determines the delay time. It becomes possible.
さらに、ｎ個のトランスファーゲートのオン抵抗値をそ
れぞれ適切な値に設定することにより、もっと微細な遅
延時間の調整が可能となる。Further, by setting the on-resistance values of the n transfer gates to appropriate values, it is possible to more finely adjust the delay time.
第１図は本発明の一実施例の回路図、第２図は従来のＣ
ＭＯＳ遅延回路の一例の回路図である。
２・・・ＣＭＯＳインｏ−インバー３・・・直列抵抗、
４１〜４ｎ・・・トランスファーゲート、８・・・ＭＯ
８キャパシタ、９・・・ｃｈｉｏｓインバータ回パーＴ
ｌ ・・・入力端子 ）１１ｏ・・・出力部子。
代理人 弁理士 内 原 晋
± １ 図
ｆｆ１２ 図FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional C
FIG. 3 is a circuit diagram of an example of a MOS delay circuit. 2...CMOS ino-invar 3...Series resistance,
41-4n...Transfer gate, 8...MO
8 capacitors, 9...chios inverter times par T
l...Input terminal) 11o...Output part. Agent Patent Attorney Susumu Uchihara 1 Figure ff12 Figure
Claims (1)
パシタの積分回路を有するＣＭＯＳ遅延回路において、
前記直列抵抗に複数のトランスファーゲートを並列に設
けたことを特徴とするＣＭＯＳ遅延回路。In a CMOS delay circuit that has an integrating circuit of a series resistor and a MOS capacitor between two CMOS inverters,
A CMOS delay circuit characterized in that a plurality of transfer gates are provided in parallel to the series resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1097932A JPH02274121A (en) | 1989-04-17 | 1989-04-17 | Cmos delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1097932A JPH02274121A (en) | 1989-04-17 | 1989-04-17 | Cmos delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02274121A true JPH02274121A (en) | 1990-11-08 |
Family
ID=14205448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1097932A Pending JPH02274121A (en) | 1989-04-17 | 1989-04-17 | Cmos delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02274121A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007509541A (en) * | 2003-10-16 | 2007-04-12 | インテル・コーポレーション | Adaptive input / output buffer and method thereof |
| JP2009253881A (en) * | 2008-04-10 | 2009-10-29 | Nec Electronics Corp | Semiconductor device, and timing adjusting method for semiconductor device |
| JP2013183381A (en) * | 2012-03-02 | 2013-09-12 | Nec Network Products Ltd | Semiconductor device, method for controlling semiconductor integrated circuit, and program of the same |
-
1989
- 1989-04-17 JP JP1097932A patent/JPH02274121A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007509541A (en) * | 2003-10-16 | 2007-04-12 | インテル・コーポレーション | Adaptive input / output buffer and method thereof |
| JP2009253881A (en) * | 2008-04-10 | 2009-10-29 | Nec Electronics Corp | Semiconductor device, and timing adjusting method for semiconductor device |
| JP2013183381A (en) * | 2012-03-02 | 2013-09-12 | Nec Network Products Ltd | Semiconductor device, method for controlling semiconductor integrated circuit, and program of the same |
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